Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.29 95.29

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.30 92.30
tb.dut.top_earlgrey.u_edn0 95.03 95.03


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.30 92.30


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.30 92.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.03 95.03


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.03 95.03


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1210 1153 95.29
Total Bits 0->1 605 578 95.54
Total Bits 1->0 605 575 95.04

Ports 78 63 80.77
Port Bits 1210 1153 95.29
Port Bits 0->1 605 578 95.54
Port Bits 1->0 605 575 95.04

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T5,*T17,*T19 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T5,*T17,*T19 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T136,T59,T137 Yes T136,T59,T137 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T143,T75,T407 Yes T143,T75,T407 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T136,T59,T137 Yes T136,T59,T137 OUTPUT
edn_o[0].edn_fips Yes Yes T80,T81,T182 Yes T83,T143,T134 OUTPUT
edn_o[0].edn_ack Yes Yes T136,T59,T137 Yes T136,T59,T137 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T143,T193,T194 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_fips Yes Yes T72,T84,T85 Yes T72,T75,T86 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T143,T75,T407 Yes T143,T75,T407 OUTPUT
edn_o[3].edn_fips No No Yes T143,T75,T407 OUTPUT
edn_o[3].edn_ack Yes Yes T143,T75,T407 Yes T143,T75,T407 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T17,T114,T189 Yes T6,T17,T114 OUTPUT
edn_o[4].edn_fips No No Yes T84,T408,T85 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T5,T6,T31 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T81,T84,T409 Yes T143,T134,T410 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T80,T81,T182 Yes T83,T143,T183 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T5,T17,T19 Yes T5,T6,T31 OUTPUT
edn_o[7].edn_fips Yes Yes T72,T80,T81 Yes T82,T72,T143 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T72,T80,T182 Yes T82,T72,T83 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T81,T411,T84 Yes T81,T411,T84 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T181,T110,T373 Yes T181,T110,T373 INPUT
alert_rx_i[1].ping_n Yes Yes T110,T163,T103 Yes T110,T163,T164 INPUT
alert_rx_i[1].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T184,T163 Yes T110,T184,T163 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T181,T110,T373 Yes T181,T110,T373 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T186,T364,T187 Yes T186,T364,T187 OUTPUT
intr_edn_fatal_err_o Yes Yes T186,T187,T188 Yes T186,T187,T188 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 714 659 92.30
Total Bits 0->1 357 330 92.44
Total Bits 1->0 357 329 92.16

Ports 50 37 74.00
Port Bits 714 659 92.30
Port Bits 0->1 357 330 92.44
Port Bits 1->0 357 329 92.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_mask[3:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_valid Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_o.a_ready Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T72,*T148,*T149 Yes T82,T72,T83 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T72,T148,T149 Yes T82,T72,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
edn_i[0].edn_req Yes Yes T83,T143,T183 Yes T83,T143,T183 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T83,T143,T183 Yes T83,T143,T183 OUTPUT
edn_o[0].edn_fips Yes Yes T80,T81,T182 Yes T83,T143,T183 OUTPUT
edn_o[0].edn_ack Yes Yes T83,T143,T183 Yes T83,T143,T183 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T72,T83,T143 Yes T82,T72,T83 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T82,T72,T83 Yes T72,T83,T143 INPUT
csrng_cmd_i.genbits_fips No No Yes T80,T182,T412 INPUT
csrng_cmd_i.genbits_valid Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T84,T409,T408 Yes T84,T409,T408 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T163,T121 Yes T110,T163,T121 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T181,T110,T413 Yes T181,T110,T413 INPUT
alert_rx_i[1].ping_n Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_rx_i[1].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T164 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T163,T121 Yes T110,T163,T121 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T181,T110,T413 Yes T181,T110,T413 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T186,T364,T187 Yes T186,T364,T187 OUTPUT
intr_edn_fatal_err_o Yes Yes T186,T187,T188 Yes T186,T187,T188 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 61 78.21
Total Bits 1208 1148 95.03
Total Bits 0->1 604 576 95.36
Total Bits 1->0 604 572 94.70

Ports 78 61 78.21
Port Bits 1208 1148 95.03
Port Bits 0->1 604 576 95.36
Port Bits 1->0 604 572 94.70

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T17,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T82,T72,T83 Yes T82,T72,T83 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 OUTPUT
tl_o.d_user.data_intg[1] No No No OUTPUT
tl_o.d_user.data_intg[6:2] Yes Yes T82,T72,T83 Yes T82,T72,T83 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T5,*T17,*T19 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T5,*T17,*T19 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T82,*T72,*T83 Yes T82,T72,T83 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T136,T59,T137 Yes T136,T59,T137 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T143,T75,T407 Yes T143,T75,T407 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T136,T59,T137 Yes T136,T59,T137 OUTPUT
edn_o[0].edn_fips No No Yes T143,T134,T135 OUTPUT
edn_o[0].edn_ack Yes Yes T136,T59,T137 Yes T136,T59,T137 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T143,T193,T194 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_fips Yes Yes T72,T84,T85 Yes T72,T75,T86 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T143,T75,T407 Yes T143,T75,T407 OUTPUT
edn_o[3].edn_fips No No Yes T143,T75,T407 OUTPUT
edn_o[3].edn_ack Yes Yes T143,T75,T407 Yes T143,T75,T407 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T17,T114,T189 Yes T6,T17,T114 OUTPUT
edn_o[4].edn_fips No No Yes T84,T408,T85 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T5,T6,T31 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T81,T84,T409 Yes T143,T134,T410 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T80,T81,T182 Yes T83,T143,T183 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T5,T17,T19 Yes T5,T6,T31 OUTPUT
edn_o[7].edn_fips Yes Yes T72,T80,T81 Yes T82,T72,T143 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T5,T17,T19 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T72,T80,T182 Yes T82,T72,T83 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T81,T411,T84 Yes T81,T411,T84 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_n Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[0].ping_p Yes Yes T110,T184,T163 Yes T110,T184,T163 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T110,T373,T163 Yes T110,T373,T163 INPUT
alert_rx_i[1].ping_n Yes Yes T110,T163,T103 Yes T110,T163,T164 INPUT
alert_rx_i[1].ping_p Yes Yes T110,T163,T164 Yes T110,T163,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T110,T184,T163 Yes T110,T184,T163 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T110,T373,T163 Yes T110,T373,T163 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T186,T364,T187 Yes T186,T364,T187 OUTPUT
intr_edn_fatal_err_o Yes Yes T186,T187,T188 Yes T186,T187,T188 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%