Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3619851	1			T78	38		T79	3160		T80	108
values[2]	720047	1			T78	17		T79	421		T80	91
values[3]	99175	1			T78	4		T79	4		T82	6
values[4]	52578	1			T79	1		T532	74		T756	12
values[5]	35486	1			T79	4		T532	52		T756	12
values[6]	26749	1			T79	4		T532	38		T756	12
values[7]	21635	1			T79	3		T532	22		T756	12
values[8]	18711	1			T79	2		T532	14		T756	12
values[9]	16312	1			T79	2		T532	17		T756	13
values[10]	15497	1			T79	1		T532	15		T756	12
values[11]	14192	1			T79	1		T532	16		T756	12
values[12]	13482	1			T79	4		T532	25		T756	12
values[13]	12745	1			T79	3		T532	27		T756	12
values[14]	11900	1			T79	2		T532	27		T756	12
values[15]	11762	1			T79	5		T532	20		T756	12
values[16]	11388	1			T79	2		T532	19		T756	12
values[17]	10882	1			T79	1		T532	7		T756	12
values[18]	10385	1			T79	6		T532	4		T756	14
values[19]	9894	1			T79	3		T532	7		T756	12
values[20]	9603	1			T79	1		T532	8		T756	12
values[21]	9259	1			T79	1		T532	6		T756	12
values[22]	9064	1			T79	4		T532	10		T756	12
values[23]	8971	1			T79	3		T532	8		T756	12
values[24]	8553	1			T79	1		T532	3		T756	12
values[25]	8525	1			T79	1		T532	12		T756	12
values[26]	8170	1			T79	1		T532	18		T756	12
values[27]	7647	1			T79	3		T532	8		T756	12
values[28]	7379	1			T79	2		T532	12		T756	12
values[29]	6793	1			T79	1		T532	14		T756	12
values[30]	6497	1			T79	1		T532	3		T756	12
values[31]	6028	1			T79	3		T532	2		T756	12
values[32]	5739	1			T79	3		T532	3		T756	13
values[33]	5194	1			T79	3		T532	5		T756	12
values[34]	4654	1			T79	2		T532	4		T756	12
values[35]	4450	1			T79	3		T532	4		T756	12
values[36]	4284	1			T79	1		T532	6		T756	12
values[37]	4100	1			T79	5		T532	7		T756	12
values[38]	3827	1			T79	2		T532	1		T756	12
values[39]	3517	1			T79	1		T532	1		T756	12
values[40]	3596	1			T79	1		T532	1		T756	12
values[41]	3376	1			T79	1		T532	1		T756	12
values[42]	3269	1			T79	1		T532	2		T756	13
values[43]	3212	1			T79	1		T532	1		T756	12
values[44]	3044	1			T79	1		T532	2		T756	12
values[45]	3048	1			T79	1		T532	3		T756	12
values[46]	2984	1			T79	1		T532	6		T756	12
values[47]	3019	1			T79	2		T532	1		T756	12
values[48]	2946	1			T79	2		T532	1		T756	12
values[49]	2921	1			T79	2		T532	2		T756	12
values[50]	2908	1			T79	5		T532	3		T756	12
values[51]	2894	1			T79	2		T532	2		T756	12
values[52]	2766	1			T79	1		T532	3		T756	12
values[53]	2673	1			T79	1		T532	3		T756	12
values[54]	2647	1			T79	2		T532	5		T756	12
values[55]	2608	1			T79	4		T532	1		T756	12
values[56]	2576	1			T79	1		T532	4		T756	12
values[57]	2505	1			T79	1		T532	1		T756	12
values[58]	2456	1			T79	2		T756	12		T539	20
values[59]	2433	1			T79	1		T756	12		T539	19
values[60]	2485	1			T79	1		T756	12		T539	19
values[61]	2708	1			T79	1		T756	12		T539	19
values[62]	3839	1			T79	1		T756	12		T539	20
values[63]	9683	1			T79	2		T756	13		T539	21
values[64]	237603	1			T79	37		T756	2349		T539	3427

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4638752	1			T78	248		T79	4589		T80	128
values[2]	792338	1			T78	69		T79	892		T80	39
values[3]	83215	1			T78	10		T79	13		T80	5
values[4]	14616	1			T79	1		T82	2		T532	11
values[5]	5409	1			T79	4		T532	2		T756	15
values[6]	3225	1			T79	1		T756	5		T546	1
values[7]	2501	1			T79	4		T756	2		T535	18
values[8]	1986	1			T79	1		T756	2		T535	8
values[9]	1768	1			T79	2		T756	1		T535	7
values[10]	1656	1			T79	2		T756	1		T535	12
values[11]	1527	1			T79	1		T756	1		T535	4
values[12]	1395	1			T79	3		T756	1		T539	3
values[13]	1353	1			T79	1		T756	1		T539	3
values[14]	1195	1			T79	1		T756	1		T539	3
values[15]	1058	1			T79	1		T756	1		T539	3
values[16]	1067	1			T79	1		T756	1		T539	3
values[17]	960	1			T79	7		T756	1		T539	3
values[18]	868	1			T79	1		T756	1		T539	3
values[19]	795	1			T79	2		T756	1		T539	3
values[20]	790	1			T79	3		T756	1		T539	3
values[21]	803	1			T79	2		T756	1		T539	3
values[22]	769	1			T79	1		T756	1		T539	3
values[23]	698	1			T79	1		T756	1		T539	3
values[24]	696	1			T79	1		T756	1		T539	3
values[25]	733	1			T79	1		T756	1		T539	3
values[26]	728	1			T79	1		T756	1		T539	3
values[27]	710	1			T79	2		T756	1		T539	3
values[28]	725	1			T79	1		T756	1		T539	3
values[29]	608	1			T79	2		T756	1		T539	3
values[30]	653	1			T79	2		T756	1		T539	3
values[31]	615	1			T79	2		T756	1		T539	3
values[32]	635	1			T79	1		T756	1		T539	3
values[33]	575	1			T79	1		T756	1		T539	3
values[34]	550	1			T79	2		T756	1		T539	3
values[35]	526	1			T79	2		T756	1		T539	3
values[36]	522	1			T79	2		T756	1		T539	3
values[37]	550	1			T79	4		T756	1		T539	3
values[38]	532	1			T79	1		T756	1		T539	3
values[39]	520	1			T79	1		T756	1		T539	3
values[40]	486	1			T79	3		T756	1		T539	3
values[41]	505	1			T79	4		T756	1		T539	3
values[42]	484	1			T79	2		T756	1		T539	4
values[43]	477	1			T79	1		T756	1		T539	3
values[44]	458	1			T79	1		T756	1		T539	3
values[45]	445	1			T79	1		T756	1		T539	3
values[46]	449	1			T79	1		T756	1		T539	3
values[47]	465	1			T79	2		T756	1		T539	3
values[48]	428	1			T79	2		T756	1		T539	3
values[49]	426	1			T79	1		T756	1		T539	3
values[50]	413	1			T79	2		T756	1		T539	3
values[51]	406	1			T79	4		T756	1		T539	3
values[52]	430	1			T79	5		T756	1		T539	3
values[53]	415	1			T79	1		T756	1		T539	3
values[54]	450	1			T79	1		T756	1		T539	3
values[55]	402	1			T79	1		T756	1		T539	3
values[56]	392	1			T79	1		T756	1		T539	3
values[57]	421	1			T79	1		T756	1		T539	3
values[58]	364	1			T79	1		T756	1		T539	3
values[59]	350	1			T79	1		T756	1		T539	3
values[60]	384	1			T79	1		T756	1		T539	3
values[61]	425	1			T79	3		T756	1		T539	3
values[62]	728	1			T79	3		T756	1		T539	3
values[63]	2575	1			T79	3		T756	1		T539	5
values[64]	26314	1			T79	51		T756	233		T539	502

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	556729	1			T78	7		T79	347		T80	1
values[2]	2594002	1			T78	49		T79	2500		T80	77
values[3]	1134676	1			T78	22		T79	627		T80	38
values[4]	140029	1			T78	2		T79	19		T82	2
values[5]	71779	1			T79	3		T532	62		T435	1
values[6]	46259	1			T79	1		T532	47		T756	13
values[7]	33973	1			T79	2		T532	30		T756	12
values[8]	27190	1			T79	2		T532	23		T756	12
values[9]	22704	1			T79	1		T532	24		T756	12
values[10]	19395	1			T79	1		T532	35		T756	12
values[11]	17507	1			T79	1		T532	39		T756	12
values[12]	16175	1			T79	2		T532	30		T756	12
values[13]	14914	1			T79	1		T532	24		T756	12
values[14]	14348	1			T79	3		T532	7		T756	12
values[15]	13824	1			T79	4		T532	19		T756	12
values[16]	13145	1			T79	3		T532	24		T756	12
values[17]	12831	1			T79	1		T532	29		T756	12
values[18]	12585	1			T79	1		T532	30		T756	13
values[19]	12115	1			T79	1		T532	30		T756	13
values[20]	11816	1			T79	1		T532	14		T756	12
values[21]	11387	1			T79	1		T532	14		T756	12
values[22]	10783	1			T79	2		T532	13		T756	12
values[23]	10327	1			T79	1		T532	8		T756	12
values[24]	9834	1			T79	1		T532	4		T756	12
values[25]	9420	1			T79	1		T532	9		T756	13
values[26]	9173	1			T79	1		T532	18		T756	12
values[27]	8548	1			T79	2		T532	17		T756	12
values[28]	8081	1			T79	4		T532	10		T756	12
values[29]	7407	1			T79	1		T532	10		T756	12
values[30]	6704	1			T79	2		T532	22		T756	12
values[31]	6276	1			T79	2		T532	21		T756	13
values[32]	6193	1			T79	4		T532	17		T756	12
values[33]	5852	1			T79	1		T532	10		T756	12
values[34]	5490	1			T79	2		T532	2		T756	12
values[35]	4979	1			T79	6		T532	2		T756	12
values[36]	4594	1			T79	1		T532	5		T756	12
values[37]	4291	1			T79	2		T532	2		T756	13
values[38]	4105	1			T79	1		T532	2		T756	12
values[39]	3894	1			T79	3		T532	1		T756	12
values[40]	3742	1			T79	3		T532	1		T756	13
values[41]	3659	1			T79	1		T532	1		T756	12
values[42]	3632	1			T79	1		T532	1		T756	12
values[43]	3571	1			T79	1		T532	1		T756	12
values[44]	3458	1			T79	1		T532	2		T756	12
values[45]	3509	1			T79	1		T532	2		T756	12
values[46]	3358	1			T79	3		T532	2		T756	13
values[47]	3204	1			T79	5		T532	1		T756	12
values[48]	3172	1			T79	1		T532	4		T756	12
values[49]	3212	1			T79	1		T756	12		T539	19
values[50]	3178	1			T79	2		T756	12		T539	20
values[51]	3042	1			T79	3		T756	12		T539	19
values[52]	2980	1			T79	2		T756	12		T539	19
values[53]	2959	1			T79	4		T756	13		T539	19
values[54]	3043	1			T79	9		T756	12		T539	19
values[55]	2932	1			T79	1		T756	13		T539	19
values[56]	2736	1			T79	1		T756	12		T539	19
values[57]	2758	1			T79	1		T756	12		T539	19
values[58]	2846	1			T79	2		T756	12		T539	19
values[59]	2741	1			T79	2		T756	12		T539	19
values[60]	2762	1			T79	2		T756	12		T539	19
values[61]	2819	1			T79	1		T756	13		T539	19
values[62]	3594	1			T79	1		T756	12		T539	20
values[63]	8147	1			T79	1		T756	13		T539	22
values[64]	232588	1			T79	50		T756	2178		T539	3539