Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1821190	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37208671

1

T4

21235

T5

3932

T1

8903

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27065882	1			T4	10266		T5	1153		T1	4493
values[0x0]	10542878	1			T4	10969		T5	2779		T1	4410
values[0x1]	1421101	1			T4	1910		T5	163		T1	556

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	545458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38484403

1

T4

23145

T5

4095

T1

9459

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18441542	1			T4	11573		T5	2048		T1	4730
valid_sources[0x01]	18440369	1			T4	11572		T5	2047		T1	4729
valid_sources[0x02]	38508	1			T20	3		T81	3		T8	2
valid_sources[0x03]	34598	1			T533	43		T377	211		T378	105
valid_sources[0x04]	34995	1			T19	3		T81	1		T533	14
valid_sources[0x05]	34015	1			T20	3		T62	4		T8	2
valid_sources[0x06]	33916	1			T19	2		T200	3		T533	13
valid_sources[0x07]	34013	1			T19	2		T81	4		T8	1
valid_sources[0x08]	34553	1			T20	1		T533	36		T377	187
valid_sources[0x09]	37856	1			T200	1		T533	14		T377	199
valid_sources[0x0a]	34866	1			T533	7		T377	272		T378	102
valid_sources[0x0b]	34227	1			T62	3		T8	1		T533	4
valid_sources[0x0c]	33573	1			T533	19		T377	173		T378	101
valid_sources[0x0d]	34333	1			T19	9		T20	3		T200	7
valid_sources[0x0e]	34206	1			T200	6		T8	1		T533	12
valid_sources[0x0f]	34294	1			T19	7		T8	1		T533	14
valid_sources[0x10]	33586	1			T20	2		T533	12		T377	181
valid_sources[0x11]	34402	1			T81	1		T200	4		T533	5
valid_sources[0x12]	36443	1			T81	1		T533	30		T377	215
valid_sources[0x13]	34369	1			T62	2		T533	6		T377	95
valid_sources[0x14]	34219	1			T19	4		T81	2		T533	14
valid_sources[0x15]	34920	1			T20	7		T200	1		T8	1
valid_sources[0x16]	34675	1			T19	1		T81	1		T533	3
valid_sources[0x17]	34425	1			T533	9		T377	160		T378	90
valid_sources[0x18]	34544	1			T8	1		T533	26		T377	153
valid_sources[0x19]	34113	1			T8	2		T533	17		T377	173
valid_sources[0x1a]	34412	1			T8	1		T533	18		T377	149
valid_sources[0x1b]	33979	1			T20	1		T81	2		T8	1
valid_sources[0x1c]	34490	1			T533	40		T377	153		T378	69
valid_sources[0x1d]	34002	1			T81	3		T62	3		T8	2
valid_sources[0x1e]	34678	1			T8	1		T533	10		T377	217
valid_sources[0x1f]	34330	1			T81	1		T8	1		T533	7
valid_sources[0x20]	35488	1			T62	1		T8	1		T533	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26460055

1

T4

10266

T5

1153

T1

4493

values[0x0]

all_enables

biggest_size

10499641

1

T4

10969

T5

2779

T1

4410

values[0x1]

all_enables

biggest_size

248975

1

T19

22

T20

21

T81

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2862029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

451079

1

T78

6

T79

500

T80

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1122503	1			T78	19		T79	1262		T80	75
values[0x0]	1070056	1			T78	23		T79	1229		T80	63
values[0x1]	1120549	1			T78	16		T79	1248		T80	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2215656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1097452

1

T78

19

T79

1229

T80

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51617	1			T78	2		T79	23		T80	4
valid_sources[0x01]	51129	1			T79	24		T83	27		T247	1
valid_sources[0x02]	51882	1			T79	52		T83	15		T532	3
valid_sources[0x03]	53286	1			T78	1		T79	27		T80	7
valid_sources[0x04]	51730	1			T78	1		T79	44		T83	7
valid_sources[0x05]	50914	1			T78	2		T79	45		T82	1
valid_sources[0x06]	51378	1			T79	85		T83	2		T450	1
valid_sources[0x07]	51367	1			T78	1		T79	67		T80	17
valid_sources[0x08]	51456	1			T79	54		T80	3		T82	3
valid_sources[0x09]	51834	1			T78	1		T79	79		T80	1
valid_sources[0x0a]	51036	1			T79	41		T80	1		T83	35
valid_sources[0x0b]	50964	1			T79	68		T80	1		T83	10
valid_sources[0x0c]	51095	1			T79	54		T80	3		T450	2
valid_sources[0x0d]	51898	1			T78	3		T79	34		T83	8
valid_sources[0x0e]	51674	1			T79	38		T83	11		T450	3
valid_sources[0x0f]	50974	1			T79	39		T83	37		T247	2
valid_sources[0x10]	52174	1			T79	24		T80	2		T247	1
valid_sources[0x11]	51077	1			T79	21		T83	21		T450	2
valid_sources[0x12]	52352	1			T79	30		T80	9		T83	21
valid_sources[0x13]	52117	1			T79	20		T80	5		T83	12
valid_sources[0x14]	52990	1			T78	1		T79	49		T80	2
valid_sources[0x15]	53112	1			T79	150		T80	5		T83	16
valid_sources[0x16]	52086	1			T78	2		T79	132		T82	1
valid_sources[0x17]	51791	1			T78	1		T79	68		T80	1
valid_sources[0x18]	51182	1			T79	91		T80	2		T82	1
valid_sources[0x19]	51826	1			T78	3		T79	49		T80	4
valid_sources[0x1a]	51213	1			T79	43		T83	3		T247	1
valid_sources[0x1b]	52598	1			T79	76		T450	3		T532	6
valid_sources[0x1c]	52476	1			T79	43		T80	1		T83	7
valid_sources[0x1d]	51225	1			T78	10		T79	44		T83	31
valid_sources[0x1e]	51627	1			T78	12		T79	42		T82	1
valid_sources[0x1f]	51875	1			T79	46		T80	6		T82	2
valid_sources[0x20]	51867	1			T79	71		T80	1		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47014

1

T78

1

T79

44

T80

3

values[0x0]

all_enables

biggest_size

356977

1

T78

5

T79

395

T80

19

values[0x1]

all_enables

biggest_size

47088

1

T79

61

T80

3

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3059999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

497941

1

T78

51

T79

775

T80

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1216237	1			T78	111		T79	1890		T80	59
values[0x0]	1123254	1			T78	116		T79	1834		T80	54
values[0x1]	1218449	1			T78	99		T79	1928		T80	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2348623	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1209317

1

T78

107

T79

1870

T80

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55303	1			T78	2		T79	75		T80	2
valid_sources[0x01]	55320	1			T79	73		T80	4		T83	14
valid_sources[0x02]	55707	1			T78	1		T79	70		T80	3
valid_sources[0x03]	56015	1			T78	9		T79	75		T80	3
valid_sources[0x04]	54927	1			T79	88		T80	3		T82	1
valid_sources[0x05]	55265	1			T79	74		T80	3		T82	1
valid_sources[0x06]	55059	1			T78	3		T79	118		T80	3
valid_sources[0x07]	54695	1			T78	3		T79	106		T80	2
valid_sources[0x08]	56304	1			T78	1		T79	76		T80	3
valid_sources[0x09]	54659	1			T79	101		T80	10		T83	8
valid_sources[0x0a]	55298	1			T79	81		T80	5		T83	6
valid_sources[0x0b]	56461	1			T78	1		T79	82		T83	1
valid_sources[0x0c]	54816	1			T79	73		T80	9		T83	14
valid_sources[0x0d]	56549	1			T78	4		T79	98		T80	3
valid_sources[0x0e]	55787	1			T78	7		T79	62		T80	1
valid_sources[0x0f]	55641	1			T78	2		T79	132		T80	2
valid_sources[0x10]	55151	1			T78	11		T79	66		T80	1
valid_sources[0x11]	54617	1			T78	6		T79	71		T82	1
valid_sources[0x12]	56997	1			T78	7		T79	94		T80	6
valid_sources[0x13]	55435	1			T78	5		T79	72		T80	2
valid_sources[0x14]	56450	1			T78	3		T79	82		T80	1
valid_sources[0x15]	56150	1			T79	115		T80	8		T83	19
valid_sources[0x16]	55909	1			T78	2		T79	108		T80	1
valid_sources[0x17]	55486	1			T78	9		T79	81		T80	2
valid_sources[0x18]	54855	1			T78	2		T79	83		T80	1
valid_sources[0x19]	55622	1			T78	33		T79	88		T80	4
valid_sources[0x1a]	56085	1			T78	6		T79	93		T80	1
valid_sources[0x1b]	56444	1			T79	85		T83	17		T247	1
valid_sources[0x1c]	55363	1			T78	1		T79	85		T80	3
valid_sources[0x1d]	55791	1			T78	14		T79	72		T80	5
valid_sources[0x1e]	54874	1			T78	15		T79	65		T80	2
valid_sources[0x1f]	55284	1			T78	7		T79	77		T80	7
valid_sources[0x20]	56040	1			T78	6		T79	99		T80	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51701

1

T78

7

T79

76

T82

1

values[0x0]

all_enables

biggest_size

393905

1

T78

42

T79

627

T80

21

values[0x1]

all_enables

biggest_size

52335

1

T78

2

T79

72

T80

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2887848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458534

1

T78

14

T79

481

T80

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1132186	1			T78	31		T79	1252		T80	34
values[0x0]	1082375	1			T78	25		T79	1163		T80	41
values[0x1]	1131821	1			T78	22		T79	1220		T80	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1109982

1

T78

23

T79

1208

T80

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51853	1			T79	39		T80	6		T83	14
valid_sources[0x01]	51698	1			T79	38		T80	2		T83	16
valid_sources[0x02]	52471	1			T79	48		T80	4		T83	12
valid_sources[0x03]	52578	1			T79	42		T83	18		T532	2
valid_sources[0x04]	52003	1			T78	1		T79	56		T80	1
valid_sources[0x05]	51909	1			T79	59		T80	1		T83	23
valid_sources[0x06]	51811	1			T78	1		T79	61		T80	1
valid_sources[0x07]	51643	1			T78	1		T79	63		T80	2
valid_sources[0x08]	52223	1			T78	1		T79	38		T80	2
valid_sources[0x09]	51536	1			T79	58		T83	14		T247	1
valid_sources[0x0a]	51968	1			T79	41		T80	4		T83	18
valid_sources[0x0b]	52681	1			T79	40		T80	3		T83	13
valid_sources[0x0c]	51682	1			T79	57		T80	6		T83	10
valid_sources[0x0d]	53792	1			T79	40		T83	8		T450	4
valid_sources[0x0e]	52618	1			T79	39		T80	4		T82	3
valid_sources[0x0f]	52175	1			T79	74		T82	2		T83	21
valid_sources[0x10]	51959	1			T78	1		T79	36		T80	1
valid_sources[0x11]	52046	1			T79	47		T83	19		T450	1
valid_sources[0x12]	53791	1			T78	1		T79	57		T80	6
valid_sources[0x13]	53044	1			T78	3		T79	43		T83	18
valid_sources[0x14]	52302	1			T79	53		T80	2		T83	15
valid_sources[0x15]	52488	1			T79	95		T83	18		T248	3
valid_sources[0x16]	52206	1			T79	69		T80	4		T83	11
valid_sources[0x17]	52188	1			T78	1		T79	66		T83	16
valid_sources[0x18]	52259	1			T78	2		T79	58		T83	15
valid_sources[0x19]	52610	1			T78	4		T79	64		T83	14
valid_sources[0x1a]	52475	1			T78	1		T79	64		T80	1
valid_sources[0x1b]	53213	1			T78	1		T79	55		T83	14
valid_sources[0x1c]	51521	1			T79	70		T80	3		T83	15
valid_sources[0x1d]	51685	1			T78	17		T79	35		T80	3
valid_sources[0x1e]	52352	1			T78	20		T79	46		T80	2
valid_sources[0x1f]	52609	1			T79	55		T83	25		T247	1
valid_sources[0x20]	53275	1			T78	1		T79	81		T83	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47995

1

T78

1

T79

50

T83

8

values[0x0]

all_enables

biggest_size

362950

1

T78

12

T79

388

T80

13

values[0x1]

all_enables

biggest_size

47589

1

T78

1

T79

43

T80

2