Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.26	99.03	83.14	98.84		78.28	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.26	99.65	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T17,T58,T60	Yes	T17,T58,T60	INPUT
alert_req_i	Yes	Yes	T4,T295,T181	Yes	T4,T84,T295	INPUT
alert_ack_o	Yes	Yes	T4,T84,T295	Yes	T4,T84,T295	OUTPUT
alert_state_o	Yes	Yes	T4,T295,T181	Yes	T4,T84,T295	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T84,T295	Yes	T17,T84,T295	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T306,T152	Yes	T85,T152,T86	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T152,T86	Yes	T85,T306,T152	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T84,T295	Yes	T17,T84,T295	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T85,T60,T86	Yes	T85,T60,T86	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T85,T60,T86	Yes	T85,T60,T86	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
alert_req_i	Yes	Yes	T90,T92	Yes	T84,T90,T91	INPUT
alert_ack_o	Yes	Yes	T84,T90,T91	Yes	T84,T90,T91	OUTPUT
alert_state_o	Yes	Yes	T90,T92	Yes	T84,T90,T91	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T84,T85,T60	Yes	T84,T85,T60	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T84,T85,T60	Yes	T84,T85,T60	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	INPUT
alert_req_i	Yes	Yes	T295,T307,T309	Yes	T295,T305,T307	INPUT
alert_ack_o	Yes	Yes	T295,T305,T307	Yes	T295,T305,T307	OUTPUT
alert_state_o	Yes	Yes	T295,T307,T309	Yes	T295,T305,T307	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T295,T305,T85	Yes	T295,T305,T85	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T306,T152	Yes	T85,T152,T86	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T152,T86	Yes	T85,T306,T152	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T295,T305,T85	Yes	T295,T305,T85	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	INPUT
alert_req_i	Yes	Yes	T260,T704	Yes	T260,T704	INPUT
alert_ack_o	Yes	Yes	T260,T704	Yes	T260,T704	OUTPUT
alert_state_o	Yes	Yes	T260,T704	Yes	T260,T704	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T85,T60,T260	Yes	T85,T60,T260	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T152,T86	Yes	T85,T152,T86	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T152,T86	Yes	T85,T152,T86	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T85,T60,T260	Yes	T85,T60,T260	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T17,T58,T60	Yes	T17,T58,T60	INPUT
alert_req_i	Yes	Yes	T8	Yes	T8	INPUT
alert_ack_o	Yes	Yes	T8	Yes	T8	OUTPUT
alert_state_o	Yes	Yes	T8	Yes	T8	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T17,T58,T85	Yes	T17,T58,T85	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T152,T86	Yes	T85,T152,T86	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T152,T86	Yes	T85,T152,T86	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T17,T58,T85	Yes	T17,T58,T85	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
alert_test_i	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	INPUT
alert_req_i	Yes	Yes	T4,T181,T238	Yes	T4,T181,T238	INPUT
alert_ack_o	Yes	Yes	T4,T181,T238	Yes	T4,T181,T238	OUTPUT
alert_state_o	Yes	Yes	T4,T181,T238	Yes	T4,T181,T238	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i.ack_p	Yes	Yes	T4,T181,T85	Yes	T4,T181,T85	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T87	Yes	T86,T87,T261	INPUT
alert_rx_i.ping_p	Yes	Yes	T86,T87,T261	Yes	T85,T86,T87	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T4,T181,T85	Yes	T4,T181,T85	OUTPUT