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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_22

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_23

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_24

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_25

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_26

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_27

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_32

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_35

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_37

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.24 99.77 97.17 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_7
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_8
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_9
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_10
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_11
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_12
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_13
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_14
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_15
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_16
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_17
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_18
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_19
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_20
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_21
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_22
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_23
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_24
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_25
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_26
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_27
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_28
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_29
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_30
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_32
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_34
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_35
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_36
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_37
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_38
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_7
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_7
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_7
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_8
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_8
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_8
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_9
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_9
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_9
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_10
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_10
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_10
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_11
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_11
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_11
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_12
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_12
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_12
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_13
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_13
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T436

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_13
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T436
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_14
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_14
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T546

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_14
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T546
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_15
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_15
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_15
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_16
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_16
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_16
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_17
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_17
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_17
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_18
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_18
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T412

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_18
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T412
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_19
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_19
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_19
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_20
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_20
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T436

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_20
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T436
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_21
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_21
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T529

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_21
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T529
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_22
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_22
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_22
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_23
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_23
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_23
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_24
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_24
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T435,T377

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_24
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T435,T377
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_25
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_25
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T436

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_25
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T436
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_26
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_26
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_26
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_27
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_27
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_27
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_28
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_28
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T412

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_28
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T412
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_29
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_29
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T435,T544

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_29
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T435,T544
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_30
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_30
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_30
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_31
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_31
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_31
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_32
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_32
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_32
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_33
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_33
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T436

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_33
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T436
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_34
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_34
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_34
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_35
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_35
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_35
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_36
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_36
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_36
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_37
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_37
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T378

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_37
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T378
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_38
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_38
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT4,T5,T1
1CoveredT62,T377,T436

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_periph_insel_regwen_38
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T62,T377,T436
0 Covered T4,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T1
0 1 Covered T62,T377,T378
0 0 Covered T4,T5,T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%