Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523193223	59077198	0	0
DepthKnown_A	523193223	523085910	0	0
RvalidKnown_A	523193223	523085910	0	0
WreadyKnown_A	523193223	523085910	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	59077198	0	0
T1	165491	23169	0	0
T4	322054	33616	0	0
T5	70749	7304	0	0
T17	760755	89673	0	0
T18	124234	136623	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	29273	0	0
T56	127955	143460	0	0
T57	221564	233199	0	0
T89	357663	33512	0	0
T103	0	35025	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523193223	46513206	0	0
DepthKnown_A	523193223	523085910	0	0
RvalidKnown_A	523193223	523085910	0	0
WreadyKnown_A	523193223	523085910	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	46513206	0	0
T1	165491	16475	0	0
T4	322054	26735	0	0
T5	70749	5369	0	0
T17	760755	65954	0	0
T18	124234	117836	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	19637	0	0
T56	127955	124068	0	0
T57	221564	213578	0	0
T89	357663	29346	0	0
T103	0	27212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523193223	42893444	0	0
DepthKnown_A	523193223	523085910	0	0
RvalidKnown_A	523193223	523085910	0	0
WreadyKnown_A	523193223	523085910	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	42893444	0	0
T1	165491	9940	0	0
T4	322054	23759	0	0
T5	70749	4212	0	0
T17	760755	71024	0	0
T18	124234	172668	0	0
T19	116322	39	0	0
T20	114445	39	0	0
T56	127955	171474	0	0
T57	221564	271736	0	0
T89	357663	36350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523193223	36922073	0	0
DepthKnown_A	523193223	523085910	0	0
RvalidKnown_A	523193223	523085910	0	0
WreadyKnown_A	523193223	523085910	0	0
gen_passthru_fifo.paramCheckPass	1011	1011	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	36922073	0	0
T1	165491	9459	0	0
T4	322054	23145	0	0
T5	70749	4095	0	0
T17	760755	68734	0	0
T18	124234	104109	0	0
T19	116322	39	0	0
T20	114445	146	0	0
T56	127955	116081	0	0
T57	221564	210298	0	0
T89	357663	36132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	523085910	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	91374	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	91374	0	0
T1	165491	65	0	0
T4	322054	299	0	0
T5	70749	13	0	0
T17	760755	1584	0	0
T18	124234	29	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	151	0	0
T56	127955	34	0	0
T57	221564	56	0	0
T89	357663	56	0	0
T103	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	94834	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	94834	0	0
T1	165491	65	0	0
T4	322054	299	0	0
T5	70749	13	0	0
T17	760755	1584	0	0
T18	124234	29	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	151	0	0
T56	127955	34	0	0
T57	221564	56	0	0
T89	357663	56	0	0
T103	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	51859	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	51859	0	0
T1	165491	62	0	0
T4	322054	175	0	0
T5	70749	12	0	0
T17	760755	1568	0	0
T18	124234	0	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	95	0	0
T56	127955	5	0	0
T57	221564	5	0	0
T89	357663	55	0	0
T103	0	59	0	0
T114	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	51859	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	51859	0	0
T1	165491	62	0	0
T4	322054	175	0	0
T5	70749	12	0	0
T17	760755	1568	0	0
T18	124234	0	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	95	0	0
T56	127955	5	0	0
T57	221564	5	0	0
T89	357663	55	0	0
T103	0	59	0	0
T114	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	39515	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	39515	0	0
T1	165491	3	0	0
T4	322054	124	0	0
T5	70749	1	0	0
T17	760755	16	0	0
T18	124234	29	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	56	0	0
T56	127955	29	0	0
T57	221564	51	0	0
T89	357663	1	0	0
T103	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597619612	42975	0	0
DepthKnown_A	597619612	597500768	0	0
RvalidKnown_A	597619612	597500768	0	0
WreadyKnown_A	597619612	597500768	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	42975	0	0
T1	165491	3	0	0
T4	322054	124	0	0
T5	70749	1	0	0
T17	760755	16	0	0
T18	124234	29	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	56	0	0
T56	127955	29	0	0
T57	221564	51	0	0
T89	357663	1	0	0
T103	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597619612	597500768	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	116310	0	0
T20	114445	114434	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0