Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_i.a_valid	Yes	Yes	T18,T17,T89	Yes	T18,T17,T89	INPUT
tl_o.a_ready	Yes	Yes	T18,T17,T89	Yes	T18,T17,T89	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T17,T89	Yes	T18,T17,T89	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T17,T89	Yes	T18,T17,T89	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T8,*T78	Yes	T81,T8,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T89,*T56	Yes	T18,T89,T56	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T17,T89	Yes	T18,T17,T89	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T85,T733	Yes	T17,T85,T733	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T85,T733	Yes	T17,T85,T733	OUTPUT
cio_rx_i	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
cio_tx_o	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T89,T139,T317	Yes	T89,T139,T317	OUTPUT
intr_tx_empty_o	Yes	Yes	T89,T139,T317	Yes	T89,T139,T317	OUTPUT
intr_rx_watermark_o	Yes	Yes	T89,T139,T317	Yes	T89,T139,T317	OUTPUT
intr_tx_done_o	Yes	Yes	T89,T139,T317	Yes	T89,T139,T317	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T139,T317	Yes	T89,T139,T317	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_i.a_valid	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	INPUT
tl_o.a_ready	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	OUTPUT
tl_o.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T56,*T57	Yes	T18,T56,T57	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T85,T60	Yes	T17,T85,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T85,T60	Yes	T17,T85,T60	OUTPUT
cio_rx_i	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
cio_tx_o	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T88,T303,T304	Yes	T88,T303,T304	OUTPUT
intr_tx_empty_o	Yes	Yes	T88,T303,T304	Yes	T88,T303,T304	OUTPUT
intr_rx_watermark_o	Yes	Yes	T88,T303,T304	Yes	T88,T303,T304	OUTPUT
intr_tx_done_o	Yes	Yes	T88,T303,T329	Yes	T88,T303,T329	OUTPUT
intr_rx_overflow_o	Yes	Yes	T88,T303,T329	Yes	T88,T303,T329	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_i.a_valid	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	INPUT
tl_o.a_ready	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T89,*T317,*T304	Yes	T89,T317,T304	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T85,T60	Yes	T17,T85,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T85,T60	Yes	T17,T85,T60	OUTPUT
cio_rx_i	Yes	Yes	T89,T46,T317	Yes	T89,T21,T46	INPUT
cio_tx_o	Yes	Yes	T89,T317,T111	Yes	T89,T317,T111	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
intr_tx_empty_o	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
intr_rx_watermark_o	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
intr_tx_done_o	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_i.a_valid	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	INPUT
tl_o.a_ready	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T8,*T78	Yes	T81,T8,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T139,*T304,*T313	Yes	T139,T304,T313	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T85,T734	Yes	T17,T85,T734	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T85,T734	Yes	T17,T85,T734	OUTPUT
cio_rx_i	Yes	Yes	T139,T140,T330	Yes	T139,T140,T330	INPUT
cio_tx_o	Yes	Yes	T139,T140,T330	Yes	T139,T140,T330	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
intr_tx_empty_o	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
intr_rx_watermark_o	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
intr_tx_done_o	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
intr_rx_overflow_o	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_i.a_valid	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	INPUT
tl_o.a_ready	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T27,*T28,*T304	Yes	T27,T28,T304	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T85,T733	Yes	T17,T85,T733	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T85,T733	Yes	T17,T85,T733	OUTPUT
cio_rx_i	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
cio_tx_o	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
intr_tx_empty_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
intr_rx_watermark_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
intr_tx_done_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
intr_rx_overflow_o	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T304,T313,T314	Yes	T304,T313,T314	OUTPUT

*Tests covering at least one bit in the range