Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
clk_usb_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_main_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
rst_fixed_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
rst_usb_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T78,T79,T82	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T82,T247,T248	Yes	T82,T247,T248	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T18,T100,T70	Yes	T18,T100,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T100	Yes	T4,T18,T100	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T20,T81,T200	Yes	T20,T81,T200	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T20,T81,T200	Yes	T20,T81,T200	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T19,T20,T66	Yes	T19,T20,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T19,*T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T19,T20,T70	Yes	T19,T20,T70	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T79,T82	Yes	T8,T79,T82	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T8,*T78,T79	Yes	T8,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T8,T78,T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T8,*T78,*T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T8,T78,T79	Yes	T8,T78,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T70,*T255,*T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T70,*T255,*T256	Yes	T70,T255,T256	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T18,T17	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T70,T255,T256	Yes	T70,T255,T256	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T61,T243	Yes	T60,T61,T243	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T8,*T78,*T79	Yes	T8,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T402,T403,T404	Yes	T402,T403,T404	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T79,T80	Yes	T60,T61,T243	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T402,T403,T404	Yes	T402,T60,T61	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T8,*T79,*T80	Yes	T8,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T267,*T392,*T404	Yes	T402,T267,T392	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T402,T267,T60	Yes	T402,T267,T60	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_peri_i.d_error	Yes	Yes	T4,T98,T300	Yes	T4,T98,T300	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_peri_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T25,T196,T199	Yes	T25,T196,T199	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T210,T24,T381	Yes	T210,T24,T381	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T210,T290	Yes	T17,T210,T60	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T210,T24,T381	Yes	T210,T24,T381	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T210,*T290,*T24	Yes	T210,T290,T24	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T210,T46,T381	Yes	T210,T46,T381	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T46,T290	Yes	T210,T46,T60	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T210,T46,T381	Yes	T210,T46,T381	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T210,*T46,*T290	Yes	T210,T46,T290	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T210,T46,T60	Yes	T210,T46,T60	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	INPUT
tl_usbdev_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T30,T210,T242	Yes	T30,T210,T242	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T210,T242	Yes	T30,T210,T242	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T30,T210	Yes	T30,T210,T242	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T30,*T210	Yes	T30,T210,T242	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T30,T210	Yes	T1,T30,T210	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T78,T79,T82	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T79,T82,T83	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T97,T296,T301	Yes	T97,T296,T301	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_hmac_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T18,*T56,*T57	Yes	T18,T56,T57	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T448,T109,T118	Yes	T448,T109,T118	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T448,T109,T118	Yes	T448,T109,T118	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T62,*T78,*T79	Yes	T62,T78,T79	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T448,T109,T289	Yes	T448,T109,T289	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	INPUT
tl_kmac_i.d_error	Yes	Yes	T79,T80,T83	Yes	T79,T80,T83	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T448,T109,T118	Yes	T45,T448,T109	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	INPUT
tl_kmac_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T62,*T79,*T82	Yes	T62,T79,T80	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T448,*T109,*T118	Yes	T448,T109,T168	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T45,T448,T109	Yes	T45,T448,T109	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	INPUT
tl_aes_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T83	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	INPUT
tl_aes_i.d_sink	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T723,*T690,*T120	Yes	T723,T690,T120	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T723,T690,T120	Yes	T723,T690,T120	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T82,T83	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T18,*T118,*T119	Yes	T18,T56,T57	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T118,T438,T690	Yes	T118,T438,T690	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_csrng_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T118,T438,T690	Yes	T118,T438,T690	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_csrng_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T118,*T438,*T690	Yes	T118,T438,T690	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T118,T690,T119	Yes	T118,T690,T119	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T118,T690,T119	Yes	T118,T690,T119	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_edn0_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T118,T690,T119	Yes	T118,T690,T119	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_edn0_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T82,T83	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T118,*T690,*T119	Yes	T118,T690,T119	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_edn1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T79,T82,T83	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T118,*T119,*T120	Yes	T118,T119,T120	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T1,T18	Yes	T4,T5,T1	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T79,T82,T83	Yes	T79,T80,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T82,T83	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T17	Yes	T4,T1,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T19,*T20,*T200	Yes	T19,T20,T200	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T19,*T20,*T200	Yes	T19,T20,T200	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T94,T171,T58	Yes	T94,T171,T58	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_keymgr_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T56,T58,T118	Yes	T56,T58,T118	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T18,*T56,*T57	Yes	T18,T56,T57	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T8,*T79,*T80	Yes	T8,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T8,T78,T79	Yes	T8,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T8,*T79,*T82	Yes	T8,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T79,T82,T83	Yes	T78,T79,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T428,*T441,*T78	Yes	T428,T441,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T80,T82	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T100,T184,T294	Yes	T100,T184,T294	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T100,T181	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T18,T100,T181	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T428,T441,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T100,*T181,*T110	Yes	T100,T442,T181	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range