Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
rst_peri_ni	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_main_o.d_error	Yes	Yes	T4,T98,T300	Yes	T4,T98,T300	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_main_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	INPUT
tl_uart0_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	INPUT
tl_uart0_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T18,*T56,*T57	Yes	T18,T56,T57	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T18,T17,T56	Yes	T18,T17,T56	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	INPUT
tl_uart1_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T89,T317,T304	Yes	T89,T317,T304	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	INPUT
tl_uart1_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T89,*T317,*T304	Yes	T89,T317,T304	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T17,T89,T317	Yes	T17,T89,T317	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	INPUT
tl_uart2_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T139,T304,T313	Yes	T139,T304,T313	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	INPUT
tl_uart2_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T78	Yes	T81,T8,T78	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T139,*T304,*T313	Yes	T139,T304,T313	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T17,T139,T304	Yes	T17,T139,T304	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	INPUT
tl_uart3_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T27,T28,T304	Yes	T27,T28,T304	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	INPUT
tl_uart3_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T27,*T28,*T304	Yes	T27,T28,T304	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T210,T212,T381	Yes	T210,T212,T381	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T210,T212,T381	Yes	T210,T212,T381	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_i2c0_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T212,T315,T318	Yes	T212,T315,T318	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T210,T212	Yes	T17,T210,T60	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T17,T210,T212	Yes	T17,T210,T60	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T210,*T212,*T381	Yes	T210,T212,T381	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T210,T381,T320	Yes	T210,T381,T320	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T210,T381,T320	Yes	T210,T381,T320	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_i2c1_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T320,T332,T315	Yes	T320,T332,T315	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T210,T381	Yes	T17,T210,T60	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T17,T210,T381	Yes	T17,T210,T60	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T79,T80,T82	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T210,*T381,*T320	Yes	T210,T381,T320	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T210,T381,T327	Yes	T210,T381,T327	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T210,T381,T327	Yes	T210,T381,T327	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_i2c2_i.d_error	Yes	Yes	T79,T80,T83	Yes	T79,T80,T83	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T327,T321,T334	Yes	T327,T321,T334	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T210,T381	Yes	T17,T210,T60	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T17,T210,T381	Yes	T17,T210,T60	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T210,*T381,*T327	Yes	T210,T381,T327	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T17,T210,T60	Yes	T17,T210,T60	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T149,T346,T150	Yes	T149,T346,T150	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T149,T346,T150	Yes	T149,T346,T150	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T60,T149,T346	Yes	T60,T149,T346	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T60,T149,T346	Yes	T60,T149,T346	INPUT
tl_pattgen_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T149,T346,T150	Yes	T149,T346,T150	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T346,T150	Yes	T60,T149,T346	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T149,T346,T150	Yes	T60,T149,T346	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T62,T79,T80	Yes	T62,T79,T80	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T149,*T346,*T150	Yes	T149,T346,T150	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T60,T149,T346	Yes	T60,T149,T346	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T141,T142,T725	Yes	T141,T142,T725	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T141,T142,T725	Yes	T141,T142,T725	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T60,T141,T142	Yes	T60,T141,T142	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T60,T141,T142	Yes	T60,T141,T142	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T141,T142,T725	Yes	T141,T142,T725	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T141,T142,T725	Yes	T60,T141,T142	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T141,T142,T725	Yes	T60,T141,T142	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T82	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T8,T78,*T79	Yes	T8,T78,T79	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T141,*T142,*T725	Yes	T141,T142,T725	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T60,T141,T142	Yes	T60,T141,T142	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_gpio_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T82,T83	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T141,T36,T142	Yes	T60,T141,T36	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T141,T36,T142	Yes	T60,T141,T36	INPUT
tl_gpio_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T82,T83	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T18,*T17	Yes	T4,T5,T1	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T210,T88,T51	Yes	T210,T88,T51	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T210,T88,T51	Yes	T210,T88,T51	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T210,T88,T60	Yes	T210,T88,T60	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T210,T88,T60	Yes	T210,T88,T60	INPUT
tl_spi_device_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T210,T88,T51	Yes	T210,T88,T51	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T88,T51	Yes	T210,T88,T51	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T210,T88,T60	Yes	T210,T88,T51	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T210,*T88,*T60	Yes	T210,T88,T51	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T210,T88,T60	Yes	T210,T88,T60	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T736,T141,T252	Yes	T736,T141,T252	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T736,T141,T252	Yes	T736,T141,T252	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T736,T60,T141	Yes	T736,T60,T141	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T736,T60,T141	Yes	T736,T60,T141	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T736,T252,T149	Yes	T736,T252,T149	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T736,T141,T252	Yes	T736,T60,T141	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T736,T141,T252	Yes	T736,T60,T141	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T736,*T141,*T252	Yes	T736,T141,T252	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T736,T60,T141	Yes	T736,T60,T141	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T79,T82,T83	Yes	T78,T79,T82	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T78,*T79	Yes	T8,T78,T79	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T82	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T18,*T17	Yes	T1,T18,T17	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T18,T17	Yes	T1,T18,T17	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T78,*T79	Yes	T8,T78,T79	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T80	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T89,T296	Yes	T5,T89,T296	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T89,T97	Yes	T5,T89,T97	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T89,T297	Yes	T5,T89,T297	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T1	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T1	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T89,*T296	Yes	T5,T89,T296	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T79,T82,T83	Yes	T78,T79,T82	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T82,T83	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T62,*T8,*T79	Yes	T62,T8,T79	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T145,*T146,*T147	Yes	T145,T146,T147	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T17,*T100,*T148	Yes	T17,T100,T148	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T62,T79,T80	Yes	T62,T79,T80	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T62,T79,T80	Yes	T62,T79,T80	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T62,T79,T80	Yes	T62,T79,T80	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T62,T78,T79	Yes	T62,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T78,T79	Yes	T62,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T62,T79,T82	Yes	T62,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T18,T17	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T62,T79,T80	Yes	T62,T79,T80	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T79,T83,T247	Yes	T78,T79,T83	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T63,T64,T65	Yes	T63,T64,T60	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T89,T56	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T70,*T255,*T256	Yes	T70,T255,T256	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T18,*T100,*T70	Yes	T18,T89,T56	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T18,T89,T56	Yes	T18,T89,T56	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T57,T103	Yes	T1,T57,T103	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T57,T103	Yes	T1,T57,T103	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T1,T17	Yes	T4,T5,T1	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T17	Yes	T4,T5,T1	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T79,T80,T83	Yes	T79,T80,T83	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T82	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T18,*T17	Yes	T4,T18,T17	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T78,T79,T82	Yes	T78,T79,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T181,T110,T182	Yes	T181,T110,T182	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T181,T110	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T18,T181,T110	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T181,*T110,*T182	Yes	T442,T181,T110	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T18,T56,T57	Yes	T18,T56,T57	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T1	Yes	T4,T18,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T18,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T19,*T20,*T200	Yes	T19,T20,T200	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T1	Yes	T4,T5,T1	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T17	Yes	T4,T1,T17	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T428,T441,T78	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T1,*T18	Yes	T4,T1,T18	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T1,T18	Yes	T4,T1,T18	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T79,T82,T450	Yes	T79,T80,T82	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T114,T31	Yes	T1,T114,T31	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T114,T203,T31	Yes	T1,T114,T203	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T8,*T79	Yes	T81,T8,T79	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T114,*T31	Yes	T1,T114,T203	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T1,T114,T203	Yes	T1,T114,T203	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T79,T82,T83	Yes	T79,T82,T83	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T95,T2	Yes	T1,T95,T6	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T79,*T82,*T83	Yes	T79,T80,T82	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T95,*T2	Yes	T1,T95,T6	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T1,T95,T6	Yes	T1,T95,T6	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	T19,T20,*T70	Yes	T19,T20,T70	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T19,T20,T81	Yes	T19,T20,T81	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
tl_ast_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T18,T17	Yes	T4,T5,T1	INPUT
tl_ast_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T82	Yes	T78,T79,T80	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T78,T79,T82	Yes	T78,T79,T80	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T1	Yes	T4,T5,T1	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range