Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T286,T287
0	1	Covered	T185,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T286,T287
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T185,T286,T287

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1046386446	1031659776	0	0
CheckNGreaterZero_A	2022	2022	0	0
GntImpliesReady_A	1046386446	8388	0	0
GntImpliesValid_A	1046386446	8388	0	0
GrantKnown_A	1046386446	1031659776	0	0
IdxKnown_A	1046386446	1031659776	0	0
IndexIsCorrect_A	1046386446	8388	0	0
NoReadyValidNoGrant_A	1046386446	0	0	0
Priority_A	1046386446	8388	0	0
ReadyAndValidImplyGrant_A	1046386446	8388	0	0
ReqAndReadyImplyGrant_A	1046386446	8388	0	0
ReqImpliesValid_A	1046386446	8388	0	0
ValidKnown_A	1046386446	1031659776	0	0
gen_data_port_assertion.DataFlow_A	1046386446	8388	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	1031659776	0	0
T1	330982	330858	0	0
T4	644108	643876	0	0
T5	141498	141382	0	0
T17	1521510	1520912	0	0
T18	248468	248446	0	0
T19	232644	0	0	0
T20	228890	0	0	0
T45	0	446702	0	0
T56	255910	255900	0	0
T57	443128	443118	0	0
T89	715326	715210	0	0
T103	0	580442	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2022	2022	0	0
T1	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T56	2	2	0	0
T57	2	2	0	0
T89	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	1031659776	0	0
T1	330982	330858	0	0
T4	644108	643876	0	0
T5	141498	141382	0	0
T17	1521510	1520912	0	0
T18	248468	248446	0	0
T19	232644	0	0	0
T20	228890	0	0	0
T45	0	446702	0	0
T56	255910	255900	0	0
T57	443128	443118	0	0
T89	715326	715210	0	0
T103	0	580442	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	1031659776	0	0
T1	330982	330858	0	0
T4	644108	643876	0	0
T5	141498	141382	0	0
T17	1521510	1520912	0	0
T18	248468	248446	0	0
T19	232644	0	0	0
T20	228890	0	0	0
T45	0	446702	0	0
T56	255910	255900	0	0
T57	443128	443118	0	0
T89	715326	715210	0	0
T103	0	580442	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	1031659776	0	0
T1	330982	330858	0	0
T4	644108	643876	0	0
T5	141498	141382	0	0
T17	1521510	1520912	0	0
T18	248468	248446	0	0
T19	232644	0	0	0
T20	228890	0	0	0
T45	0	446702	0	0
T56	255910	255900	0	0
T57	443128	443118	0	0
T89	715326	715210	0	0
T103	0	580442	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046386446	8388	0	0
T113	428650	0	0	0
T141	508720	0	0	0
T143	286174	0	0	0
T144	853112	0	0	0
T179	104566	0	0	0
T185	165126	2797	0	0
T286	0	2794	0	0
T287	0	2797	0	0
T392	473636	0	0	0
T393	558502	0	0	0
T394	256666	0	0	0
T395	290580	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T286,T287
0	1	Covered	T185,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T286,T287
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T185,T286,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	523193223	515829888	0	0
CheckNGreaterZero_A	1011	1011	0	0
GntImpliesReady_A	523193223	5198	0	0
GntImpliesValid_A	523193223	5198	0	0
GrantKnown_A	523193223	515829888	0	0
IdxKnown_A	523193223	515829888	0	0
IndexIsCorrect_A	523193223	5198	0	0
NoReadyValidNoGrant_A	523193223	0	0	0
Priority_A	523193223	5198	0	0
ReadyAndValidImplyGrant_A	523193223	5198	0	0
ReqAndReadyImplyGrant_A	523193223	5198	0	0
ReqImpliesValid_A	523193223	5198	0	0
ValidKnown_A	523193223	515829888	0	0
gen_data_port_assertion.DataFlow_A	523193223	5198	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	5198	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1734	0	0
T286	0	1730	0	0
T287	0	1734	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T286,T287
0	1	Covered	T185,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T286,T287
1	Covered	T185,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T286,T287
1	0	Covered	T185,T286,T287
1	1	Covered	T185,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T185,T286,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T286,T287
0	Covered	T185,T286,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	523193223	515829888	0	0
CheckNGreaterZero_A	1011	1011	0	0
GntImpliesReady_A	523193223	3190	0	0
GntImpliesValid_A	523193223	3190	0	0
GrantKnown_A	523193223	515829888	0	0
IdxKnown_A	523193223	515829888	0	0
IndexIsCorrect_A	523193223	3190	0	0
NoReadyValidNoGrant_A	523193223	0	0	0
Priority_A	523193223	3190	0	0
ReadyAndValidImplyGrant_A	523193223	3190	0	0
ReqAndReadyImplyGrant_A	523193223	3190	0	0
ReqImpliesValid_A	523193223	3190	0	0
ValidKnown_A	523193223	515829888	0	0
gen_data_port_assertion.DataFlow_A	523193223	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	515829888	0	0
T1	165491	165429	0	0
T4	322054	321938	0	0
T5	70749	70691	0	0
T17	760755	760456	0	0
T18	124234	124223	0	0
T19	116322	0	0	0
T20	114445	0	0	0
T45	0	223351	0	0
T56	127955	127950	0	0
T57	221564	221559	0	0
T89	357663	357605	0	0
T103	0	290221	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523193223	3190	0	0
T113	214325	0	0	0
T141	254360	0	0	0
T143	143087	0	0	0
T144	426556	0	0	0
T179	52283	0	0	0
T185	82563	1063	0	0
T286	0	1064	0	0
T287	0	1063	0	0
T392	236818	0	0	0
T393	279251	0	0	0
T394	128333	0	0	0
T395	145290	0	0	0