Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522223568	59010119	0	0
DepthKnown_A	522223568	522116776	0	0
RvalidKnown_A	522223568	522116776	0	0
WreadyKnown_A	522223568	522116776	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	59010119	0	0
T5	228662	23451	0	0
T6	77512	8072	0	0
T17	81171	8737	0	0
T18	108510	9882	0	0
T19	150551	20074	0	0
T26	382630	11998	0	0
T45	370934	53667	0	0
T59	221943	233674	0	0
T97	66506	7635	0	0
T166	92161	11015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522223568	46341481	0	0
DepthKnown_A	522223568	522116776	0	0
RvalidKnown_A	522223568	522116776	0	0
WreadyKnown_A	522223568	522116776	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	46341481	0	0
T5	228662	19521	0	0
T6	77512	6211	0	0
T17	81171	6452	0	0
T18	108510	7396	0	0
T19	150551	14998	0	0
T26	382630	9149	0	0
T45	370934	45327	0	0
T59	221943	214063	0	0
T97	66506	5116	0	0
T166	92161	8483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522223568	43245757	0	0
DepthKnown_A	522223568	522116776	0	0
RvalidKnown_A	522223568	522116776	0	0
WreadyKnown_A	522223568	522116776	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	43245757	0	0
T5	228662	21739	0	0
T6	77512	4878	0	0
T17	81171	7552	0	0
T18	108510	5278	0	0
T19	150551	8808	0	0
T26	382630	6807	0	0
T45	370934	39696	0	0
T59	221943	266787	0	0
T97	66506	3609	0	0
T166	92161	6051	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522223568	37113282	0	0
DepthKnown_A	522223568	522116776	0	0
RvalidKnown_A	522223568	522116776	0	0
WreadyKnown_A	522223568	522116776	0	0
gen_passthru_fifo.paramCheckPass	1001	1001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	37113282	0	0
T5	228662	21535	0	0
T6	77512	4750	0	0
T17	81171	7192	0	0
T18	108510	5126	0	0
T19	150551	8540	0	0
T26	382630	6635	0	0
T45	370934	39217	0	0
T59	221943	210960	0	0
T97	66506	3450	0	0
T166	92161	5892	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522223568	522116776	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1001	1001	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	91495	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	91495	0	0
T5	228662	53	0	0
T6	77512	13	0	0
T17	81171	14	0	0
T18	108510	21	0	0
T19	150551	26	0	0
T26	382630	12	0	0
T45	370934	75	0	0
T59	221943	56	0	0
T97	66506	13	0	0
T166	92161	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	95114	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	95114	0	0
T5	228662	53	0	0
T6	77512	13	0	0
T17	81171	14	0	0
T18	108510	21	0	0
T19	150551	26	0	0
T26	382630	12	0	0
T45	370934	75	0	0
T59	221943	56	0	0
T97	66506	13	0	0
T166	92161	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	51681	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	51681	0	0
T5	228662	52	0	0
T6	77512	12	0	0
T17	81171	13	0	0
T18	108510	20	0	0
T19	150551	23	0	0
T26	382630	11	0	0
T45	370934	73	0	0
T59	221943	5	0	0
T97	66506	12	0	0
T166	92161	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	51681	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	51681	0	0
T5	228662	52	0	0
T6	77512	12	0	0
T17	81171	13	0	0
T18	108510	20	0	0
T19	150551	23	0	0
T26	382630	11	0	0
T45	370934	73	0	0
T59	221943	5	0	0
T97	66506	12	0	0
T166	92161	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	39814	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	39814	0	0
T5	228662	1	0	0
T6	77512	1	0	0
T17	81171	1	0	0
T18	108510	1	0	0
T19	150551	3	0	0
T26	382630	1	0	0
T45	370934	2	0	0
T59	221943	51	0	0
T97	66506	1	0	0
T166	92161	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	599299675	43433	0	0
DepthKnown_A	599299675	599180528	0	0
RvalidKnown_A	599299675	599180528	0	0
WreadyKnown_A	599299675	599180528	0	0
gen_passthru_fifo.paramCheckPass	2892	2892	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	43433	0	0
T5	228662	1	0	0
T6	77512	1	0	0
T17	81171	1	0	0
T18	108510	1	0	0
T19	150551	3	0	0
T26	382630	1	0	0
T45	370934	2	0	0
T59	221943	51	0	0
T97	66506	1	0	0
T166	92161	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	599299675	599180528	0	0
T4	38349	38291	0	0
T5	228662	228600	0	0
T6	77512	77457	0	0
T17	81171	81113	0	0
T18	108510	108455	0	0
T19	150551	150500	0	0
T26	382630	382575	0	0
T45	370934	370821	0	0
T59	221943	221938	0	0
T97	66506	66444	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2892	2892	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T97	1	1	0	0