Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.25 100.00 89.01 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc 93.88 90.91 84.62 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc 93.88 90.91 84.62 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc 93.88 90.91 84.62 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc 96.43 100.00 85.71 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc 98.08 100.00 92.31 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc 98.08 100.00 92.31 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=11,ResetVal=0,BitMask=1793,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

SCORECOND
97.73 90.91
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

SCORECOND
96.43 85.71
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT7,T8,T389

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10CoveredT1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT1,T2,T3

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

SCORECOND
93.88 84.62
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

SCORECOND
93.88 84.62
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

SCORECOND
93.88 84.62
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

SCORECOND
98.08 92.31
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT1,T3,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T6


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T4,T5,T6


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 1952654 0 0
DstReqKnown_A 45879025 40482225 0 0
SrcAckBusyChk_A 2147483647 4912 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1952654 0 0
T1 62664 1518 0 0
T2 93340 779 0 0
T3 0 2531 0 0
T9 0 1754 0 0
T11 0 1852 0 0
T13 23003 303 0 0
T14 0 837 0 0
T15 0 1309 0 0
T16 0 1326 0 0
T20 79726 0 0 0
T62 132042 0 0 0
T87 188802 3432 0 0
T111 0 629 0 0
T112 0 725 0 0
T113 38236 0 0 0
T114 120640 0 0 0
T115 94486 0 0 0
T116 328274 0 0 0
T117 120866 0 0 0
T118 104124 0 0 0
T135 691950 10352 0 0
T152 655442 7388 0 0
T153 1285410 17658 0 0
T366 614844 10898 0 0
T367 646370 6407 0 0
T375 607746 4758 0 0
T381 87274 1230 0 0
T390 1581210 821 0 0
T391 653536 2949 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 45879025 40482225 0 0
T4 8425 4075 0 0
T5 16600 12275 0 0
T6 9650 5375 0 0
T17 13575 9225 0 0
T18 11925 7650 0 0
T19 15050 10750 0 0
T26 26025 21725 0 0
T45 30550 26225 0 0
T59 117025 112725 0 0
T97 9250 4900 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4912 0 0
T1 62664 3 0 0
T2 93340 2 0 0
T3 0 6 0 0
T9 0 4 0 0
T11 0 7 0 0
T13 23003 1 0 0
T14 0 2 0 0
T15 0 4 0 0
T16 0 4 0 0
T20 79726 0 0 0
T62 132042 0 0 0
T87 188802 8 0 0
T111 0 2 0 0
T112 0 2 0 0
T113 38236 0 0 0
T114 120640 0 0 0
T115 94486 0 0 0
T116 328274 0 0 0
T117 120866 0 0 0
T118 104124 0 0 0
T135 691950 25 0 0
T152 655442 18 0 0
T153 1285410 45 0 0
T366 614844 26 0 0
T367 646370 17 0 0
T375 607746 13 0 0
T381 87274 4 0 0
T390 1581210 3 0 0
T391 653536 7 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 250375 239350 0 0
T5 1395550 1381225 0 0
T6 485650 474275 0 0
T17 661075 653200 0 0
T18 669575 660275 0 0
T19 1019000 1006650 0 0
T26 2315075 2305125 0 0
T45 2254675 2244400 0 0
T59 13338925 13326750 0 0
T97 421150 408200 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%