Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	521	1			T519	3		T670	1		T814	2
all_values[1]	479	1			T422	1		T437	1		T438	4
all_values[2]	486	1			T523	1		T412	3		T519	4
all_values[3]	526	1			T437	2		T412	3		T519	2
all_values[4]	554	1			T437	1		T519	2		T670	1
all_values[5]	458	1			T523	1		T412	1		T519	4
all_values[6]	499	1			T412	3		T519	2		T814	4
all_values[7]	516	1			T422	1		T438	1		T412	2
all_values[8]	544	1			T412	2		T519	1		T814	4
all_values[9]	484	1			T422	1		T437	1		T412	7
all_values[10]	497	1			T438	1		T523	1		T412	3
all_values[11]	511	1			T519	2		T670	1		T814	3
all_values[12]	518	1			T438	1		T412	1		T519	4
all_values[13]	485	1			T523	1		T412	1		T519	2
all_values[14]	496	1			T523	1		T412	2		T519	5
all_values[15]	507	1			T437	1		T412	2		T519	2
all_values[16]	511	1			T422	1		T437	1		T438	1
all_values[17]	497	1			T422	2		T437	1		T412	4
all_values[18]	513	1			T412	1		T519	4		T670	1
all_values[19]	515	1			T438	2		T412	2		T519	3
all_values[20]	478	1			T438	2		T523	1		T519	1
all_values[21]	489	1			T422	1		T438	2		T412	3
all_values[22]	546	1			T437	1		T438	2		T523	2
all_values[23]	529	1			T438	1		T520	1		T412	2
all_values[24]	508	1			T422	1		T437	2		T412	4
all_values[25]	495	1			T437	3		T438	1		T412	2
all_values[26]	530	1			T523	1		T412	3		T519	2
all_values[27]	497	1			T438	1		T412	2		T519	2
all_values[28]	529	1			T437	2		T412	3		T519	2
all_values[29]	525	1			T438	1		T412	1		T519	5
all_values[30]	485	1			T422	1		T437	3		T523	1
all_values[31]	539	1			T422	1		T412	4		T519	3
all_values[32]	527	1			T412	3		T519	2		T670	2
all_values[33]	527	1			T422	1		T438	1		T520	1
all_values[34]	489	1			T422	1		T520	1		T523	1
all_values[35]	460	1			T422	1		T523	1		T412	1
all_values[36]	476	1			T438	1		T520	1		T412	3
all_values[37]	498	1			T519	6		T670	1		T814	2
all_values[38]	513	1			T422	2		T437	1		T412	3
all_values[39]	489	1			T412	2		T519	4		T814	3
all_values[40]	513	1			T437	1		T412	3		T519	2
all_values[41]	527	1			T438	1		T412	4		T519	2
all_values[42]	496	1			T438	1		T412	1		T519	6
all_values[43]	498	1			T437	2		T438	1		T523	2
all_values[44]	474	1			T437	1		T519	1		T670	2
all_values[45]	517	1			T437	1		T519	2		T534	2
all_values[46]	508	1			T412	2		T519	3		T814	4
all_values[47]	479	1			T438	1		T519	5		T814	1
all_values[48]	496	1			T438	1		T412	4		T519	3
all_values[49]	433	1			T422	1		T437	1		T412	3