| | | | | | | |
tb.dut.top_earlgrey.scanmodeKnown
| 0 | 0 | 521111818 | 521111818 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A
| 0 | 0 | 1639403 | 1445641 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 130458442 | 3 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A
| 0 | 0 | 1639403 | 3944 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A
| 0 | 0 | 130458442 | 1710 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A
| 0 | 0 | 130458442 | 129784053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A
| 0 | 0 | 1639403 | 1445641 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A
| 0 | 0 | 1639403 | 1445641 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A
| 0 | 0 | 130458442 | 38599069 | 0 | 280 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A
| 0 | 0 | 130458442 | 11945442 | 0 | 15 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A
| 0 | 0 | 130458442 | 1449 | 0 | 101 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A
| 0 | 0 | 130458442 | 1449 | 0 | 101 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A
| 0 | 0 | 130458442 | 1449 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A
| 0 | 0 | 130458442 | 261 | 0 | 202 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A
| 0 | 0 | 130458442 | 35579765 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129777195 | 0 | 3000 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129777195 | 0 | 3000 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129777195 | 0 | 3000 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129777195 | 0 | 3000 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A
| 0 | 0 | 130458442 | 129784159 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 804 | 679 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 1751 | 751 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit
| 0 | 0 | 151335880 | 609147 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv
| 0 | 0 | 151335880 | 609147 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse
| 0 | 0 | 151335880 | 480750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 139993 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 1844028 | 25 | 0 | 972 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 1844028 | 25 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 151335880 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 1844028 | 121 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 292 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 295 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 114082 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 286 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 286 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 286 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 286 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 286 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 112662 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 283 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 283 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 283 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 283 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 283 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 103067 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 259 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 259 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 259 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 259 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 259 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 108725 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 99266 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 252 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 252 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 252 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 252 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 252 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 103131 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 102992 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 88693 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 98988 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 248 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 248 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 248 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 248 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 248 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 108583 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 269 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 269 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 269 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 270 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 117613 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 107345 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 105267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 91141 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 110911 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 278 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 278 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 278 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 278 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 278 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 103666 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 260 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 101160 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 254 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 254 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 254 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 254 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 254 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 99777 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 251 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 251 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 251 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 251 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 251 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 90346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 98227 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 244 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 244 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 244 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 244 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 246 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 96457 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 241 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 241 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 241 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 241 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 110205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 277 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 277 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 277 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 277 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 277 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 97782 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 245 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 245 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 245 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 245 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 245 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A
| 0 | 0 | 151335880 | 90570 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A
| 0 | 0 | 1844028 | 1626828 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A
| 0 | 0 | 151335880 | 150560608 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1844028 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1844028 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 151335880 | 228 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse
| 0 | 0 | 151335880 | 128397 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A
| 0 | 0 | 1639403 | 1445641 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A
| 0 | 0 | 514187433 | 7 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A
| 0 | 0 | 514187433 | 24698823 | 0 | 96 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A
| 0 | 0 | 514187433 | 65505241 | 0 | 82 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A
| 0 | 0 | 514187433 | 444042771 | 0 | 1996 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A
| 0 | 0 | 514187433 | 444044633 | 0 | 1892 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A
| 0 | 0 | 514187433 | 311 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A
| 0 | 0 | 514187433 | 587 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 514187433 | 6 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 514187433 | 40633341 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 514187433 | 34299498 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A
| 0 | 0 | 514187433 | 57911819 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A
| 0 | 0 | 514187433 | 45569027 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| 0 | 0 | 514187433 | 161 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| 0 | 0 | 514187433 | 189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs
| 0 | 0 | 514187433 | 40579793 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs
| 0 | 0 | 514187433 | 57911819 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 514187433 | 3191 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A
| 0 | 0 | 513536775 | 95484542 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A
| 0 | 0 | 514187433 | 4298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 514187433 | 4298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 514187433 | 4298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 514187433 | 4298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 514187433 | 4298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 514187433 | 506618602 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 514187433 | 5198 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A
| 0 | 0 | 514187433 | 514073215 | 0 | 2994 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 514187433 | 39 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 514187433 | 39 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 129146203 | 39 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 514187433 | 39 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A
| 0 | 0 | 514187433 | 514073215 | 0 | 2994 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit
| 0 | 0 | 597954551 | 39028 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv
| 0 | 0 | 597954551 | 39028 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse
| 0 | 0 | 597954551 | 33620 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 597954551 | 97048 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 597954551 | 100964 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 597954551 | 52884 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 597954551 | 52884 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 597954551 | 44164 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 597954551 | 48080 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 597954551 | 597835643 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse
| 0 | 0 | 597954551 | 5408 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 514187433 | 5 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A
| 0 | 0 | 514187433 | 512224544 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A
| 0 | 0 | 514187433 | 1856214 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A
| 0 | 0 | 514187433 | 512224544 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A
| 0 | 0 | 514187433 | 1856214 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete
| 0 | 0 | 514187433 | 514080758 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit
| 0 | 0 | 597954551 | 263054 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv
| 0 | 0 | 597954551 | 263054 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse
| 0 | 0 | 597954551 | 196835 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2901 | 2901 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse
| 0 | 0 | 597954551 | 66219 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 129146203 | 9 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit
| 0 | 0 | 129146203 | 5183 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv
| 0 | 0 | 129146203 | 5183 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse
| 0 | 0 | 129146203 | 3765 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse
| 0 | 0 | 129146203 | 1418 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 58 | 47 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 168 | 155 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2194 | 2177 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 749 | 731 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 56 | 43 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 145 | 131 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2193 | 2177 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 190 | 175 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 73 | 56 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 163 | 152 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2500 | 2484 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 196 | 185 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 75 | 58 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 175 | 162 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2519 | 2501 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 299 | 287 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 268 | 241 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2021 | 1996 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 266 | 239 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2021 | 1996 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 209 | 190 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 27416 | 27387 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 211 | 192 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 27419 | 27390 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 489 | 447 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 27427 | 27394 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 486 | 444 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 27428 | 27395 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 747 | 726 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2019 | 1990 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 751 | 730 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2015 | 1986 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|