Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	95.38	93.61	95.44		94.39	97.53	99.58

Total tests in report: 2901

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.03	40.03	44.95	44.95	46.51	46.51	27.62	27.62			63.07	63.07	57.87	57.87	0.14	0.14	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4219743635
47.85	7.82	49.29	4.34	56.22	9.72	27.90	0.28			69.71	6.65	83.04	25.17	0.92	0.78	/workspace/coverage/cover_reg_top/8.chip_csr_rw.955535944
55.35	7.50	58.33	9.05	59.54	3.32	30.61	2.71			69.92	0.21	83.04	0.00	30.65	29.74	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.243339829
61.09	5.74	70.83	12.50	67.52	7.98	33.49	2.88			81.02	11.10	83.04	0.00	30.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2583605667
65.65	4.55	77.87	7.04	73.26	5.74	43.78	10.29			84.16	3.14	84.09	1.05	30.71	0.06	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941997511
68.90	3.26	77.87	0.00	73.44	0.18	43.78	0.00			84.19	0.03	84.09	0.00	50.04	19.33	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1434050656
72.15	3.24	83.21	5.34	77.41	3.97	47.55	3.77			86.03	1.83	88.64	4.55	50.04	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.845525318
74.79	2.64	83.36	0.15	78.38	0.97	51.02	3.48			86.26	0.23	88.64	0.00	61.06	11.02	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1423667650
76.98	2.19	83.36	0.00	78.38	0.00	63.99	12.97			86.26	0.00	88.81	0.17	61.06	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3348622556
78.82	1.85	83.36	0.00	78.39	0.01	63.99	0.00			86.26	0.00	88.81	0.00	72.13	11.07	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2144057766
80.32	1.50	83.36	0.00	78.66	0.27	63.99	0.00			86.29	0.03	88.81	0.00	80.80	8.67	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2598760510
81.73	1.41	85.61	2.25	80.62	1.96	65.90	1.91			88.65	2.36	88.81	0.00	80.80	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.4220170552
83.01	1.28	86.88	1.27	81.11	0.49	70.72	4.82			88.87	0.22	89.69	0.87	80.80	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3414287703
84.20	1.19	86.88	0.00	81.11	0.00	77.88	7.16			88.87	0.00	89.69	0.00	80.80	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2131199615
85.34	1.13	88.23	1.35	82.22	1.11	79.24	1.36			90.05	1.18	91.43	1.75	80.85	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.928686780
86.18	0.84	88.28	0.05	82.28	0.06	81.60	2.36			90.05	0.00	91.43	0.00	83.41	2.56	/workspace/coverage/default/2.chip_sw_alert_test.2747742975
87.00	0.83	89.00	0.73	82.46	0.18	81.62	0.01			90.25	0.19	95.28	3.85	83.41	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2130725969
87.71	0.71	89.00	0.00	82.46	0.00	81.62	0.00			90.25	0.00	95.28	0.00	87.66	4.25	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1449684396
88.40	0.69	90.53	1.53	83.57	1.11	82.16	0.55			91.16	0.92	95.28	0.00	87.66	0.00	/workspace/coverage/default/2.chip_sw_gpio.277490713
89.01	0.61	90.53	0.00	83.57	0.00	82.16	0.00			91.16	0.00	95.28	0.00	91.34	3.68	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.784634812
89.59	0.58	91.26	0.73	83.74	0.17	84.58	2.42			91.16	0.00	95.28	0.00	91.51	0.16	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2063425909
90.11	0.52	92.06	0.80	85.70	1.96	84.64	0.06			91.46	0.30	95.28	0.00	91.52	0.01	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2616579134
90.63	0.51	92.07	0.01	88.36	2.66	84.64	0.00			91.46	0.00	95.28	0.00	91.93	0.41	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1679634883
91.03	0.41	92.08	0.01	88.37	0.01	87.07	2.43			91.46	0.00	95.28	0.00	91.93	0.00	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4015255968
91.41	0.38	92.64	0.56	88.89	0.52	87.67	0.60			92.05	0.58	95.28	0.00	91.93	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1696998479
91.73	0.32	93.00	0.36	89.13	0.24	88.59	0.93			92.28	0.24	95.45	0.17	91.93	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.3375016621
92.04	0.31	93.00	0.00	89.19	0.06	88.59	0.00			92.28	0.00	95.45	0.00	93.71	1.79	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.4029153591
92.34	0.30	93.00	0.00	89.19	0.00	88.59	0.00			92.28	0.00	95.45	0.00	95.51	1.80	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2153421719
92.62	0.28	93.15	0.15	89.29	0.10	89.66	1.07			92.45	0.17	95.63	0.17	95.51	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.6985687
92.82	0.20	93.15	0.00	89.35	0.06	89.66	0.00			92.45	0.00	95.63	0.00	96.67	1.16	/workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2692632470
93.01	0.19	93.46	0.31	89.55	0.20	90.00	0.34			92.75	0.29	95.63	0.00	96.69	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_output.3538066259
93.18	0.17	93.50	0.04	89.99	0.44	90.06	0.06			93.23	0.48	95.63	0.00	96.69	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2834418263
93.34	0.16	93.50	0.00	90.04	0.05	90.06	0.00			93.23	0.00	95.63	0.00	97.60	0.92	/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2085865779
93.49	0.15	93.71	0.21	90.37	0.32	90.41	0.35			93.23	0.00	95.63	0.00	97.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3568882519
93.63	0.14	93.81	0.10	90.51	0.14	90.57	0.16			93.29	0.06	95.98	0.35	97.60	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1995060230
93.76	0.14	93.81	0.00	90.51	0.00	91.38	0.81			93.29	0.00	95.98	0.00	97.60	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1719237108
93.89	0.13	93.92	0.11	90.68	0.17	91.67	0.29			93.48	0.19	95.98	0.00	97.60	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.249254373
94.01	0.12	93.93	0.01	90.68	0.00	92.34	0.67			93.48	0.00	95.98	0.00	97.65	0.05	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3090213880
94.11	0.10	93.96	0.03	90.93	0.25	92.35	0.02			93.77	0.29	95.98	0.00	97.65	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1568527089
94.20	0.10	93.96	0.00	91.08	0.15	92.35	0.00			93.80	0.03	95.98	0.00	98.05	0.40	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.608984747
94.30	0.10	93.97	0.01	91.09	0.01	92.91	0.56			93.80	0.00	95.98	0.00	98.05	0.00	/workspace/coverage/default/4.chip_sw_all_escalation_resets.202509618
94.38	0.08	94.02	0.05	91.10	0.01	92.99	0.08			93.80	0.00	96.33	0.35	98.05	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3287061075
94.46	0.08	94.02	0.00	91.56	0.46	92.99	0.00			93.80	0.00	96.33	0.00	98.05	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.117513236
94.53	0.07	94.07	0.05	91.64	0.08	93.09	0.09			93.83	0.03	96.50	0.17	98.05	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2533476201
94.60	0.07	94.07	0.00	91.64	0.00	93.48	0.39			93.83	0.00	96.50	0.00	98.05	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3178863384
94.65	0.05	94.08	0.01	91.65	0.01	93.56	0.09			93.86	0.02	96.68	0.17	98.06	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2193325643
94.70	0.05	94.11	0.03	91.69	0.03	93.60	0.04			93.89	0.03	96.85	0.17	98.06	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3854491086
94.75	0.05	94.18	0.07	91.84	0.15	93.60	0.00			93.99	0.10	96.85	0.00	98.06	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3998286445
94.80	0.04	94.18	0.00	92.02	0.18	93.60	0.00			94.00	0.02	96.85	0.00	98.12	0.06	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2378846885
94.84	0.04	94.18	0.00	92.02	0.00	93.85	0.24			94.00	0.00	96.85	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3764406872
94.87	0.04	94.20	0.03	92.02	0.01	93.85	0.01			94.01	0.01	97.03	0.17	98.13	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1435977939
94.91	0.04	94.21	0.01	92.03	0.01	93.86	0.01			94.02	0.01	97.20	0.17	98.14	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1239308047
94.95	0.04	94.21	0.01	92.04	0.01	93.87	0.01			94.03	0.01	97.38	0.17	98.16	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.534872744
94.98	0.04	94.22	0.01	92.06	0.01	93.87	0.00			94.04	0.01	97.55	0.17	98.17	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1968887292
95.02	0.04	94.22	0.00	92.06	0.00	94.08	0.21			94.04	0.00	97.55	0.00	98.17	0.00	/workspace/coverage/default/1.chip_sw_aes_masking_off.2785297480
95.05	0.03	94.22	0.00	92.06	0.01	94.08	0.00			94.04	0.00	97.55	0.00	98.37	0.20	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3641818049
95.09	0.03	94.26	0.04	92.17	0.11	94.09	0.01			94.08	0.04	97.55	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.212923837
95.12	0.03	94.33	0.07	92.17	0.00	94.19	0.11			94.09	0.01	97.55	0.00	98.37	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.2464276706
95.15	0.03	94.33	0.00	92.35	0.18	94.19	0.00			94.09	0.00	97.55	0.00	98.37	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2130110860
95.18	0.03	94.35	0.01	92.39	0.04	94.30	0.11			94.09	0.01	97.55	0.00	98.38	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3076364331
95.20	0.03	94.35	0.00	92.39	0.00	94.47	0.17			94.09	0.00	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4256554721
95.23	0.03	94.37	0.03	92.44	0.05	94.53	0.06			94.12	0.02	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2939513634
95.26	0.03	94.45	0.07	92.46	0.03	94.55	0.01			94.17	0.05	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.934190447
95.28	0.03	94.51	0.07	92.51	0.05	94.55	0.00			94.20	0.03	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2331137627
95.31	0.02	94.58	0.07	92.56	0.05	94.55	0.00			94.23	0.03	97.55	0.00	98.38	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4182350322
95.33	0.02	94.58	0.00	92.70	0.13	94.55	0.00			94.23	0.00	97.55	0.00	98.38	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3261439326
95.35	0.02	94.59	0.01	92.70	0.00	94.65	0.11			94.24	0.01	97.55	0.00	98.38	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3391980824
95.37	0.02	94.61	0.03	92.72	0.03	94.69	0.04			94.26	0.02	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.613846645
95.39	0.02	94.61	0.00	92.72	0.00	94.69	0.00			94.26	0.00	97.55	0.00	98.48	0.11	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3211207169
95.40	0.02	94.61	0.00	92.81	0.08	94.69	0.00			94.28	0.02	97.55	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/74.xbar_stress_all.4039675905
95.42	0.02	94.62	0.01	92.84	0.04	94.73	0.04			94.30	0.02	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3246764656
95.44	0.02	94.62	0.00	92.84	0.00	94.82	0.09			94.30	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.134110200
95.45	0.02	94.62	0.00	92.92	0.07	94.82	0.00			94.31	0.02	97.55	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all.2960856178
95.46	0.01	94.62	0.00	92.99	0.07	94.82	0.00			94.31	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.373545640
95.48	0.01	94.62	0.00	92.99	0.00	94.89	0.07			94.31	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3784068902
95.49	0.01	94.62	0.00	93.06	0.07	94.89	0.00			94.31	0.00	97.55	0.00	98.48	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.860868869
95.50	0.01	94.62	0.00	93.06	0.00	94.89	0.00			94.31	0.00	97.55	0.00	98.55	0.07	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.4087543152
95.51	0.01	94.62	0.00	93.06	0.00	94.96	0.07			94.31	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.765668010
95.52	0.01	94.62	0.00	93.07	0.01	94.96	0.00			94.31	0.00	97.55	0.00	98.60	0.05	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2224429090
95.53	0.01	94.62	0.00	93.07	0.00	95.02	0.06			94.31	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.233094132
95.54	0.01	94.65	0.02	93.09	0.02	95.03	0.01			94.31	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_power_sleep_load.1663379742
95.55	0.01	94.67	0.02	93.10	0.01	95.04	0.01			94.33	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3253546836
95.56	0.01	94.69	0.02	93.11	0.01	95.05	0.01			94.34	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2018533697
95.57	0.01	94.71	0.02	93.11	0.01	95.05	0.01			94.36	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3591308815
95.57	0.01	94.73	0.02	93.11	0.00	95.07	0.02			94.36	0.00	97.55	0.00	98.61	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3620124748
95.58	0.01	94.73	0.00	93.11	0.00	95.07	0.00			94.36	0.00	97.55	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2002820575
95.59	0.01	94.73	0.00	93.11	0.00	95.07	0.00			94.36	0.00	97.55	0.00	98.71	0.05	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1392227427
95.60	0.01	94.73	0.00	93.16	0.05	95.07	0.00			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.2061061520
95.60	0.01	94.73	0.00	93.21	0.05	95.07	0.00			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3336075570
95.61	0.01	94.75	0.02	93.22	0.01	95.07	0.01			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.986202518
95.62	0.01	94.75	0.00	93.22	0.00	95.12	0.04			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3901344665
95.63	0.01	94.75	0.00	93.22	0.00	95.16	0.04			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1780919362
95.63	0.01	94.76	0.01	93.23	0.01	95.18	0.02			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2320302653
95.64	0.01	94.76	0.00	93.27	0.04	95.18	0.00			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3781961041
95.64	0.01	94.76	0.00	93.30	0.04	95.18	0.00			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.534317035
95.65	0.01	94.76	0.00	93.34	0.03	95.18	0.00			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all.2439026937
95.65	0.01	94.76	0.00	93.34	0.00	95.21	0.03			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2116496576
95.66	0.01	94.76	0.00	93.34	0.00	95.24	0.03			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.459948090
95.66	0.01	94.76	0.00	93.34	0.00	95.26	0.03			94.36	0.00	97.55	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2434272322
95.67	0.01	94.76	0.00	93.34	0.01	95.26	0.00			94.36	0.00	97.55	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4258721810
95.67	0.01	94.76	0.00	93.35	0.01	95.27	0.01			94.37	0.01	97.55	0.00	98.73	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1093906181
95.68	0.01	94.76	0.00	93.37	0.01	95.27	0.00			94.37	0.00	97.55	0.00	98.74	0.01	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2330464500
95.68	0.01	94.76	0.00	93.38	0.01	95.27	0.00			94.37	0.00	97.55	0.00	98.75	0.01	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.919495702
95.68	0.01	94.76	0.01	93.40	0.01	95.27	0.01			94.37	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.186232976
95.69	0.01	94.76	0.00	93.42	0.02	95.27	0.00			94.37	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.860897348
95.69	0.01	94.77	0.01	93.42	0.00	95.29	0.01			94.37	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.113858468
95.69	0.01	94.77	0.00	93.42	0.01	95.29	0.00			94.37	0.00	97.55	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.981834228
95.70	0.01	94.77	0.00	93.42	0.00	95.31	0.02			94.37	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2872205278
95.70	0.01	94.77	0.00	93.44	0.02	95.31	0.00			94.37	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.306830571
95.70	0.01	94.77	0.00	93.44	0.00	95.31	0.01			94.37	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3593852444
95.71	0.01	94.77	0.00	93.44	0.00	95.32	0.01			94.37	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3440512289
95.71	0.01	94.77	0.00	93.44	0.00	95.33	0.02			94.37	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3276098628
95.71	0.01	94.77	0.00	93.45	0.01	95.33	0.00			94.37	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3833796256
95.71	0.01	94.77	0.00	93.45	0.01	95.33	0.00			94.37	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1340503076
95.72	0.01	94.77	0.00	93.46	0.01	95.33	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all.4106217294
95.72	0.01	94.77	0.00	93.48	0.01	95.33	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2215745662
95.72	0.01	94.77	0.00	93.49	0.01	95.33	0.00			94.37	0.00	97.55	0.00	98.81	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3056219945
95.72	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2923791818
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.867559597
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3026156027
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072940953
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4238763819
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1459145630
95.73	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1685350682
95.74	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3709641700
95.74	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3862238923
95.74	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199919790
95.74	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1990710263
95.74	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2108837413
95.75	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1665605521
95.75	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.411447307
95.75	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.605988692
95.75	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1591381544
95.75	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974742231
95.76	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2014650300
95.76	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3812364589
95.76	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1799108413
95.76	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1083780291
95.76	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792707902
95.77	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3312766337
95.77	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1485366113
95.77	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.436144075
95.77	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856157195
95.77	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2869525906
95.78	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1470064782
95.78	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388104726
95.78	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671333728
95.78	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3215644631
95.78	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2328423422
95.79	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1145015318
95.79	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2701965834
95.79	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1918315316
95.79	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3087520329
95.79	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1431203753
95.80	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423969988
95.80	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.626168763
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95.80	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2025312735
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95.81	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2483392703
95.81	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.33	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1621958253
95.81	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.34	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.872545682
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95.82	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.38	0.01	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462043548
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95.84	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.1402560299
95.84	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2959585627
95.85	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.520318487
95.85	0.01	94.77	0.00	93.49	0.00	95.33	0.00			94.37	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2757924092
95.85	0.01	94.77	0.00	93.50	0.01	95.34	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3672902807
95.85	0.01	94.77	0.00	93.50	0.00	95.35	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4010428704
95.85	0.01	94.77	0.00	93.51	0.01	95.35	0.00			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3361281114
95.86	0.01	94.77	0.00	93.52	0.01	95.35	0.00			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3897863230
95.86	0.01	94.77	0.01	93.52	0.00	95.36	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2350806679
95.86	0.01	94.78	0.01	93.52	0.01	95.36	0.00			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3288492407
95.86	0.01	94.79	0.01	93.52	0.00	95.36	0.00			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.236462573
95.86	0.01	94.79	0.00	93.52	0.00	95.36	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3003621501
95.86	0.01	94.79	0.00	93.52	0.00	95.37	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2263980483
95.87	0.01	94.79	0.00	93.52	0.00	95.38	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2776219086
95.87	0.01	94.79	0.00	93.52	0.00	95.39	0.01			94.37	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4239879380
95.87	0.01	94.79	0.00	93.52	0.00	95.39	0.00			94.38	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1585876830
95.87	0.01	94.79	0.00	93.52	0.00	95.39	0.00			94.39	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4278576936
95.87	0.01	94.79	0.00	93.52	0.00	95.39	0.00			94.39	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.2109013545
95.87	0.01	94.79	0.00	93.53	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1396888115
95.87	0.01	94.79	0.00	93.54	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/21.xbar_same_source.925352230
95.87	0.01	94.79	0.00	93.54	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2997213746
95.88	0.01	94.79	0.00	93.55	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3034598402
95.88	0.01	94.79	0.00	93.56	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.3756525640
95.88	0.01	94.79	0.00	93.57	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2608245764
95.88	0.01	94.79	0.00	93.57	0.01	95.39	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_gpio.956990474
95.88	0.01	94.79	0.00	93.57	0.00	95.40	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2280947734
95.88	0.01	94.79	0.01	93.58	0.01	95.40	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3782040285
95.88	0.01	94.80	0.01	93.58	0.00	95.40	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1926572689
95.88	0.01	94.80	0.00	93.58	0.00	95.40	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2022078460
95.88	0.01	94.80	0.00	93.58	0.00	95.41	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.968254411
95.89	0.01	94.80	0.00	93.58	0.00	95.41	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.2225008660
95.89	0.01	94.80	0.00	93.58	0.00	95.42	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.4238551327
95.89	0.01	94.80	0.00	93.58	0.00	95.42	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2381455379
95.89	0.01	94.80	0.00	93.58	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2878041225
95.89	0.01	94.80	0.00	93.58	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3693546894
95.89	0.01	94.80	0.00	93.58	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1370840679
95.89	0.01	94.80	0.00	93.59	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1149005622
95.89	0.01	94.80	0.00	93.59	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1993053945
95.89	0.01	94.80	0.00	93.59	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3714860235
95.89	0.01	94.80	0.00	93.60	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3150469205
95.89	0.01	94.80	0.00	93.60	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4282371263
95.89	0.01	94.80	0.00	93.60	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1674694079
95.89	0.01	94.80	0.00	93.61	0.01	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3877513517
95.89	0.01	94.80	0.00	93.61	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3292056294
95.89	0.01	94.80	0.01	93.61	0.00	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1923077820
95.89	0.01	94.81	0.01	93.61	0.00	95.43	0.00			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3560548018
95.90	0.01	94.81	0.00	93.61	0.00	95.43	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2452765645
95.90	0.01	94.81	0.00	93.61	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2517462731
95.90	0.01	94.81	0.00	93.61	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2262267018
95.90	0.01	94.81	0.00	93.61	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3118098407
95.90	0.01	94.81	0.00	93.61	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1910804533
95.90	0.01	94.81	0.00	93.61	0.00	95.44	0.01			94.39	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692724216

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1965962869
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.840573309
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3199204818
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3847809759
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2519100762
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.67667266
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1724202730
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1624344847
/workspace/coverage/cover_reg_top/0.xbar_error_random.1427556420
/workspace/coverage/cover_reg_top/0.xbar_random.1972686131
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3856486936
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2434733500
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2409179126
/workspace/coverage/cover_reg_top/0.xbar_same_source.794070868
/workspace/coverage/cover_reg_top/0.xbar_smoke.2215737270
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1866755654
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2039182662
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2933516258
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3729250486
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.497684039
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3203394455
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3905207091
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2517924769
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1435161780
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1532412315
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2064415809
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2279411350
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2302820817
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4183905073
/workspace/coverage/cover_reg_top/1.chip_tl_errors.151395816
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2342576491
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3545934189
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2298716559
/workspace/coverage/cover_reg_top/1.xbar_error_random.3526256952
/workspace/coverage/cover_reg_top/1.xbar_random.845509740
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2520293368
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4023296105
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.71263722
/workspace/coverage/cover_reg_top/1.xbar_same_source.691655731
/workspace/coverage/cover_reg_top/1.xbar_smoke.3582015142
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4051906674
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1768990619
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3062313566
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3924635236
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.698432730
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1869909877
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.406054876
/workspace/coverage/cover_reg_top/10.chip_csr_rw.919847698
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2841566877
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3230830739
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2819321371
/workspace/coverage/cover_reg_top/10.xbar_error_random.199445583
/workspace/coverage/cover_reg_top/10.xbar_random.1713952220
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1792604672
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3874212142
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1121084663
/workspace/coverage/cover_reg_top/10.xbar_same_source.95920097
/workspace/coverage/cover_reg_top/10.xbar_smoke.3783528157
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4204363636
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.42000763
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3788175804
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4084908029
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1083216869
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1030845772
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3595636793
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3214795019
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1287705528
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.411833554
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.523054277
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.30436574
/workspace/coverage/cover_reg_top/11.xbar_error_random.765300673
/workspace/coverage/cover_reg_top/11.xbar_random.4208771853
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1163623891
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2658363646
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3955047135
/workspace/coverage/cover_reg_top/11.xbar_same_source.1362128076
/workspace/coverage/cover_reg_top/11.xbar_smoke.2785063868
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.424565394
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3971503850
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2844958975
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3238065962
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4164695049
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2196393255
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3207421072
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3871707389
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.766630166
/workspace/coverage/cover_reg_top/12.chip_tl_errors.813325495
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2750588869
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3935469368
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1472798144
/workspace/coverage/cover_reg_top/12.xbar_error_random.3598439305
/workspace/coverage/cover_reg_top/12.xbar_random.2664461140
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1106346622
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1694706697
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3479030405
/workspace/coverage/cover_reg_top/12.xbar_same_source.3522571890
/workspace/coverage/cover_reg_top/12.xbar_smoke.3338601763
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2653071136
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1201345775
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.632160384
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3060528086
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3243848268
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.407520825
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2176048206
/workspace/coverage/cover_reg_top/13.chip_csr_rw.814630904
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3671181536
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3577510329
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1886502008
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2943991909
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1999296300
/workspace/coverage/cover_reg_top/13.xbar_error_random.3776449143
/workspace/coverage/cover_reg_top/13.xbar_random.460775701
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2143607448
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1396121677
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.285484806
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/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.191228800
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/workspace/coverage/default/2.chip_sw_rv_timer_irq.682539552
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3922553944
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2686639794
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4204199078
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2689955784
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4146797594
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3474195328
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.891526016
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1010169790
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1160674814
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1870696795
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1985823034
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3454253093
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2293794511
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1076808966
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4151805280
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3782154840
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2627534383
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3698862450
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/workspace/coverage/default/20.chip_sw_all_escalation_resets.4184336013
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.634658734
/workspace/coverage/default/30.chip_sw_all_escalation_resets.607202350
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2662992216
/workspace/coverage/default/32.chip_sw_all_escalation_resets.158172339
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2598761672
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2957989763
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.197355849
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1580721341
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3101559530
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3247123305
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2449023747
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297584808
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2116386717
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3474061726
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3915330957
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1645683704
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1442036933
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2932205418
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2602134120
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.575647689
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.771333865
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3651862894
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4168388294
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.794528546
/workspace/coverage/default/4.chip_tap_straps_dev.1368850506
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.2789920431
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.17509616
/workspace/coverage/default/41.chip_sw_all_escalation_resets.19682356
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2283016911
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1625267811
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400824870
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894929876
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1673457938
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1916681761
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1174881820
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1922946450
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294592068
/workspace/coverage/default/49.chip_sw_all_escalation_resets.831974451
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289368220
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2942558410
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.375281099
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1233821385
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.375940877
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1009830906
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489602358
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.428522082
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180627017
/workspace/coverage/default/52.chip_sw_all_escalation_resets.729195040
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1668216787
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2181049975
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.715550867
/workspace/coverage/default/54.chip_sw_all_escalation_resets.748981100
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.748725732
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3647596080
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3163218569
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3824490360
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302359121
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.900927091
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1375328795
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.383182747
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3609697110
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2648713601
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1876108385
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2426947241
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2612560085
/workspace/coverage/default/60.chip_sw_all_escalation_resets.969750689
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227757263
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2375730496
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538385746
/workspace/coverage/default/64.chip_sw_all_escalation_resets.971977669
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2400655348
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398462328
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.673236681
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679018048
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4049286456
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.116795811
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332682330
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3258414016
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1072930336
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1881914954
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1504088892
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533299421
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1903767929
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929690985
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2312504184
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098423881
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3484831217
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2906954573
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3530437892
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1804816822
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4229909145
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.400452023
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2551017663
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2930717853
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366745669
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1705319757
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3587234739
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3289919372
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4229780547
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3301232279
/workspace/coverage/default/80.chip_sw_all_escalation_resets.551040122
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.308357907
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3700824590
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.71137709
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1214834962
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1923572601
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463215475
/workspace/coverage/default/84.chip_sw_all_escalation_resets.546538423
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880552706
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2795093234
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1293704287
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2635823533
/workspace/coverage/default/87.chip_sw_all_escalation_resets.797210914
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3630130640
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183230269
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3094676862
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.721100031
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3541626037
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2435582103
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3221994864
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2539579015
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2182397763
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2461482976
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2425800479
/workspace/coverage/default/97.chip_sw_all_escalation_resets.926368381
/workspace/coverage/default/98.chip_sw_all_escalation_resets.933664117
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1096271074
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4187978890
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1269597952
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1536929195
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1334382520
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.883886572
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.303771018
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1069938928
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1394743178

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Total test records in report: 2901

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.935274910			Jul 04 08:04:11 PM PDT 24	Jul 04 08:16:01 PM PDT 24	10285063704 ps
T5	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3414287703			Jul 04 08:06:33 PM PDT 24	Jul 04 08:47:36 PM PDT 24	11471612089 ps
T6	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1083780291			Jul 04 08:14:54 PM PDT 24	Jul 04 08:21:09 PM PDT 24	3219648824 ps
T22	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4219743635			Jul 04 08:04:56 PM PDT 24	Jul 04 08:09:25 PM PDT 24	2775393714 ps
T18	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2086465686			Jul 04 08:11:38 PM PDT 24	Jul 04 08:14:47 PM PDT 24	2836572008 ps
T60	/workspace/coverage/default/3.chip_tap_straps_rma.2464276706			Jul 04 08:11:26 PM PDT 24	Jul 04 08:32:01 PM PDT 24	11077702154 ps
T19	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4204199078			Jul 04 08:01:53 PM PDT 24	Jul 04 08:21:04 PM PDT 24	9214834992 ps
T52	/workspace/coverage/default/1.chip_sw_spi_device_tpm.35048602			Jul 04 07:54:44 PM PDT 24	Jul 04 07:59:57 PM PDT 24	3800175672 ps
T86	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4015255968			Jul 04 08:13:15 PM PDT 24	Jul 04 09:11:41 PM PDT 24	16529677034 ps
T44	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.680669615			Jul 04 08:08:31 PM PDT 24	Jul 04 08:26:02 PM PDT 24	11658427852 ps
T62	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3276098628			Jul 04 07:53:48 PM PDT 24	Jul 04 07:57:24 PM PDT 24	2899209216 ps
T45	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2181049975			Jul 04 08:18:05 PM PDT 24	Jul 04 08:26:58 PM PDT 24	5153699600 ps
T250	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2463215475			Jul 04 08:20:07 PM PDT 24	Jul 04 08:26:23 PM PDT 24	4287047848 ps
T152	/workspace/coverage/default/1.rom_keymgr_functest.2645929952			Jul 04 08:01:42 PM PDT 24	Jul 04 08:11:17 PM PDT 24	4551601946 ps
T217	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941997511			Jul 04 08:17:53 PM PDT 24	Jul 04 08:25:12 PM PDT 24	4000689446 ps
T375	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1918315316			Jul 04 08:16:52 PM PDT 24	Jul 04 08:23:51 PM PDT 24	3843239280 ps
T125	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3348622556			Jul 04 07:48:53 PM PDT 24	Jul 04 08:29:46 PM PDT 24	12192165338 ps
T661	/workspace/coverage/default/1.chip_sw_aes_masking_off.2785297480			Jul 04 07:54:24 PM PDT 24	Jul 04 07:59:12 PM PDT 24	3092214087 ps
T376	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2193325643			Jul 04 08:11:47 PM PDT 24	Jul 04 08:17:39 PM PDT 24	3989521336 ps
T58	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2415591463			Jul 04 07:55:53 PM PDT 24	Jul 04 08:56:26 PM PDT 24	14801273638 ps
T114	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1017613669			Jul 04 07:49:28 PM PDT 24	Jul 04 07:54:32 PM PDT 24	2708981023 ps
T327	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2894672580			Jul 04 07:56:10 PM PDT 24	Jul 04 08:31:10 PM PDT 24	7896144202 ps
T153	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1243499553			Jul 04 08:03:46 PM PDT 24	Jul 04 08:08:56 PM PDT 24	3032030172 ps
T122	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3784068902			Jul 04 08:08:58 PM PDT 24	Jul 04 08:25:24 PM PDT 24	8152861660 ps
T67	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3076364331			Jul 04 08:17:23 PM PDT 24	Jul 04 08:26:00 PM PDT 24	4660800460 ps
T61	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1839449631			Jul 04 07:56:42 PM PDT 24	Jul 04 08:05:48 PM PDT 24	4454970490 ps
T189	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1803447483			Jul 04 07:50:01 PM PDT 24	Jul 04 07:59:02 PM PDT 24	4422063544 ps
T112	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4745089			Jul 04 08:07:46 PM PDT 24	Jul 04 08:28:45 PM PDT 24	8444336317 ps
T315	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1174881820			Jul 04 08:19:24 PM PDT 24	Jul 04 08:26:44 PM PDT 24	3690302344 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.928686780			Jul 04 07:48:54 PM PDT 24	Jul 04 08:22:34 PM PDT 24	26875715618 ps
T102	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1431203753			Jul 04 08:16:50 PM PDT 24	Jul 04 08:24:10 PM PDT 24	3847294820 ps
T103	/workspace/coverage/default/0.chip_sw_hmac_enc.2225008660			Jul 04 07:50:55 PM PDT 24	Jul 04 07:56:36 PM PDT 24	2838459646 ps
T59	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2199102754			Jul 04 08:08:04 PM PDT 24	Jul 04 09:26:34 PM PDT 24	14626668810 ps
T104	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1590667378			Jul 04 08:07:48 PM PDT 24	Jul 04 08:14:08 PM PDT 24	3151565880 ps
T20	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3500704884			Jul 04 08:04:17 PM PDT 24	Jul 04 08:17:12 PM PDT 24	9784360120 ps
T79	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1268257166			Jul 04 07:52:28 PM PDT 24	Jul 04 07:58:38 PM PDT 24	3379831730 ps
T105	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1218993847			Jul 04 08:17:01 PM PDT 24	Jul 04 08:24:13 PM PDT 24	3615948188 ps
T106	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1802500015			Jul 04 07:49:58 PM PDT 24	Jul 04 08:18:13 PM PDT 24	7678574628 ps
T107	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4079059240			Jul 04 08:14:54 PM PDT 24	Jul 04 08:21:35 PM PDT 24	4131982750 ps
T158	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2381455379			Jul 04 07:49:58 PM PDT 24	Jul 04 07:51:42 PM PDT 24	2540765269 ps
T255	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1297877756			Jul 04 08:07:11 PM PDT 24	Jul 04 09:19:06 PM PDT 24	21841573800 ps
T166	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3833160816			Jul 04 07:47:10 PM PDT 24	Jul 04 08:06:02 PM PDT 24	8319398616 ps
T21	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.6985687			Jul 04 07:49:42 PM PDT 24	Jul 04 07:52:37 PM PDT 24	3102006615 ps
T118	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1586145735			Jul 04 07:59:24 PM PDT 24	Jul 04 08:11:05 PM PDT 24	4368706350 ps
T870	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1500724780			Jul 04 07:50:07 PM PDT 24	Jul 04 07:55:48 PM PDT 24	2517823060 ps
T256	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1835081848			Jul 04 07:52:44 PM PDT 24	Jul 04 09:28:50 PM PDT 24	22241409456 ps
T113	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3901344665			Jul 04 07:50:22 PM PDT 24	Jul 04 08:22:48 PM PDT 24	11397557409 ps
T242	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294592068			Jul 04 08:17:49 PM PDT 24	Jul 04 08:25:06 PM PDT 24	3802768516 ps
T215	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3620124748			Jul 04 08:14:20 PM PDT 24	Jul 04 08:21:21 PM PDT 24	4942954728 ps
T251	/workspace/coverage/default/1.chip_sw_aon_timer_irq.211201415			Jul 04 07:53:53 PM PDT 24	Jul 04 08:00:32 PM PDT 24	3261885400 ps
T63	/workspace/coverage/default/2.chip_sw_alert_test.2747742975			Jul 04 08:07:01 PM PDT 24	Jul 04 08:13:32 PM PDT 24	3518016810 ps
T216	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.249254373			Jul 04 07:48:35 PM PDT 24	Jul 04 08:12:16 PM PDT 24	13475276633 ps
T294	/workspace/coverage/default/0.chip_sw_example_concurrency.3329346426			Jul 04 07:48:06 PM PDT 24	Jul 04 07:51:46 PM PDT 24	2196743800 ps
T295	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.308357907			Jul 04 08:21:00 PM PDT 24	Jul 04 08:26:52 PM PDT 24	3466344860 ps
T296	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001787238			Jul 04 08:15:59 PM PDT 24	Jul 04 08:22:25 PM PDT 24	3591310900 ps
T190	/workspace/coverage/default/3.chip_tap_straps_prod.4126253674			Jul 04 08:11:31 PM PDT 24	Jul 04 08:15:17 PM PDT 24	3023494585 ps
T147	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4153418484			Jul 04 08:10:28 PM PDT 24	Jul 04 08:23:05 PM PDT 24	4165476610 ps
T313	/workspace/coverage/default/2.chip_plic_all_irqs_20.2583605667			Jul 04 08:08:35 PM PDT 24	Jul 04 08:24:26 PM PDT 24	5073955744 ps
T70	/workspace/coverage/default/2.chip_jtag_mem_access.4105785150			Jul 04 08:01:00 PM PDT 24	Jul 04 08:26:01 PM PDT 24	13502930322 ps
T363	/workspace/coverage/default/27.chip_sw_all_escalation_resets.436144075			Jul 04 08:16:18 PM PDT 24	Jul 04 08:27:19 PM PDT 24	5840560956 ps
T440	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1972260625			Jul 04 07:52:32 PM PDT 24	Jul 04 08:14:00 PM PDT 24	7897440772 ps
T394	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183230269			Jul 04 08:19:28 PM PDT 24	Jul 04 08:26:20 PM PDT 24	4500146168 ps
T708	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2025312735			Jul 04 08:16:40 PM PDT 24	Jul 04 08:22:12 PM PDT 24	4373499832 ps
T163	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1651151012			Jul 04 07:58:55 PM PDT 24	Jul 04 08:51:43 PM PDT 24	11588349264 ps
T55	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1247814833			Jul 04 07:57:26 PM PDT 24	Jul 04 09:21:54 PM PDT 24	23396527830 ps
T213	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3440512289			Jul 04 08:21:17 PM PDT 24	Jul 04 08:30:47 PM PDT 24	5055587472 ps
T733	/workspace/coverage/default/2.chip_sw_aes_masking_off.2943327967			Jul 04 08:05:11 PM PDT 24	Jul 04 08:09:20 PM PDT 24	3011683096 ps
T214	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4238763819			Jul 04 08:22:23 PM PDT 24	Jul 04 08:33:31 PM PDT 24	5474676424 ps
T364	/workspace/coverage/default/94.chip_sw_all_escalation_resets.520318487			Jul 04 08:21:12 PM PDT 24	Jul 04 08:29:54 PM PDT 24	4642539668 ps
T127	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4062495669			Jul 04 07:58:24 PM PDT 24	Jul 04 08:06:47 PM PDT 24	4957720046 ps
T66	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3764406872			Jul 04 07:57:53 PM PDT 24	Jul 04 08:11:31 PM PDT 24	5895297560 ps
T116	/workspace/coverage/default/0.rom_volatile_raw_unlock.502424515			Jul 04 07:53:23 PM PDT 24	Jul 04 07:55:14 PM PDT 24	2222909892 ps
T434	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3336269765			Jul 04 08:08:06 PM PDT 24	Jul 04 08:13:22 PM PDT 24	2804905010 ps
T871	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3188455804			Jul 04 07:58:17 PM PDT 24	Jul 04 08:02:00 PM PDT 24	3488847417 ps
T368	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1488544955			Jul 04 07:49:58 PM PDT 24	Jul 04 08:01:08 PM PDT 24	6162114952 ps
T435	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4256554721			Jul 04 07:50:17 PM PDT 24	Jul 04 08:07:34 PM PDT 24	5860449520 ps
T73	/workspace/coverage/default/4.chip_tap_straps_dev.1368850506			Jul 04 08:12:39 PM PDT 24	Jul 04 08:23:46 PM PDT 24	6850663461 ps
T170	/workspace/coverage/default/0.chip_sw_flash_init.737365001			Jul 04 07:48:34 PM PDT 24	Jul 04 08:26:40 PM PDT 24	19006063112 ps
T117	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1876108385			Jul 04 08:11:55 PM PDT 24	Jul 04 08:29:27 PM PDT 24	11406689903 ps
T108	/workspace/coverage/default/1.chip_sw_power_sleep_load.1663379742			Jul 04 08:00:07 PM PDT 24	Jul 04 08:06:54 PM PDT 24	4835162106 ps
T249	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.365138858			Jul 04 08:01:12 PM PDT 24	Jul 04 08:05:47 PM PDT 24	2832969560 ps
T872	/workspace/coverage/default/2.chip_sw_uart_smoketest.1646611243			Jul 04 08:10:29 PM PDT 24	Jul 04 08:15:33 PM PDT 24	2772793568 ps
T212	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.534082484			Jul 04 07:47:30 PM PDT 24	Jul 04 08:11:02 PM PDT 24	9539908570 ps
T792	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671333728			Jul 04 08:18:28 PM PDT 24	Jul 04 08:25:21 PM PDT 24	3940010544 ps
T873	/workspace/coverage/default/2.chip_sw_aes_smoketest.649823900			Jul 04 08:11:42 PM PDT 24	Jul 04 08:16:12 PM PDT 24	3371226920 ps
T219	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3013985056			Jul 04 08:07:21 PM PDT 24	Jul 04 08:17:10 PM PDT 24	5294075420 ps
T2	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4182350322			Jul 04 08:01:44 PM PDT 24	Jul 04 08:05:46 PM PDT 24	3097060824 ps
T423	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1459145630			Jul 04 08:22:58 PM PDT 24	Jul 04 08:29:57 PM PDT 24	4064664776 ps
T424	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4286167156			Jul 04 07:50:19 PM PDT 24	Jul 04 07:57:36 PM PDT 24	3384191262 ps
T425	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.324093727			Jul 04 07:55:55 PM PDT 24	Jul 04 08:01:28 PM PDT 24	2841344210 ps
T182	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3289919372			Jul 04 08:13:57 PM PDT 24	Jul 04 08:26:47 PM PDT 24	14021675222 ps
T365	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2869525906			Jul 04 08:14:29 PM PDT 24	Jul 04 08:26:10 PM PDT 24	4353452788 ps
T56	/workspace/coverage/default/2.rom_e2e_shutdown_output.3538066259			Jul 04 08:13:23 PM PDT 24	Jul 04 09:05:09 PM PDT 24	27395337260 ps
T237	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1233821385			Jul 04 08:11:26 PM PDT 24	Jul 04 08:21:33 PM PDT 24	5163869560 ps
T31	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2781944080			Jul 04 07:47:34 PM PDT 24	Jul 04 08:17:57 PM PDT 24	8197892216 ps
T218	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3700824590			Jul 04 08:19:21 PM PDT 24	Jul 04 08:29:36 PM PDT 24	5278598056 ps
T277	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1159674123			Jul 04 07:57:27 PM PDT 24	Jul 04 09:26:14 PM PDT 24	24098744940 ps
T71	/workspace/coverage/default/0.chip_jtag_csr_rw.1926572689			Jul 04 07:41:09 PM PDT 24	Jul 04 07:57:47 PM PDT 24	10412680176 ps
T160	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3979168223			Jul 04 07:53:39 PM PDT 24	Jul 04 08:13:00 PM PDT 24	11561029378 ps
T148	/workspace/coverage/default/2.chip_sw_otbn_smoketest.1900321459			Jul 04 08:12:07 PM PDT 24	Jul 04 08:33:29 PM PDT 24	7708509264 ps
T278	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3252530021			Jul 04 08:26:14 PM PDT 24	Jul 04 08:35:10 PM PDT 24	4973487184 ps
T115	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1893622805			Jul 04 08:00:05 PM PDT 24	Jul 04 08:11:22 PM PDT 24	5177731045 ps
T173	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4146797594			Jul 04 08:09:20 PM PDT 24	Jul 04 08:21:21 PM PDT 24	7546409796 ps
T286	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1726279307			Jul 04 07:50:30 PM PDT 24	Jul 04 07:59:05 PM PDT 24	5671406070 ps
T64	/workspace/coverage/default/1.chip_jtag_csr_rw.3375016621			Jul 04 07:51:22 PM PDT 24	Jul 04 08:05:49 PM PDT 24	9639200964 ps
T49	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1999581974			Jul 04 07:56:47 PM PDT 24	Jul 04 08:08:17 PM PDT 24	6473817216 ps
T287	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3301769275			Jul 04 07:59:15 PM PDT 24	Jul 04 08:10:24 PM PDT 24	5643809679 ps
T288	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3040516447			Jul 04 07:55:42 PM PDT 24	Jul 04 08:55:49 PM PDT 24	15186619836 ps
T289	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1580721341			Jul 04 08:16:06 PM PDT 24	Jul 04 08:28:30 PM PDT 24	5463844264 ps
T257	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4184336013			Jul 04 08:15:24 PM PDT 24	Jul 04 08:24:38 PM PDT 24	5064790728 ps
T290	/workspace/coverage/default/1.chip_sw_aes_idle.1247080190			Jul 04 07:54:48 PM PDT 24	Jul 04 07:59:29 PM PDT 24	2565566000 ps
T123	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.306830571			Jul 04 07:47:43 PM PDT 24	Jul 04 08:09:16 PM PDT 24	6185003048 ps
T377	/workspace/coverage/default/60.chip_sw_all_escalation_resets.969750689			Jul 04 08:19:57 PM PDT 24	Jul 04 08:29:48 PM PDT 24	4991786708 ps
T874	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3604813157			Jul 04 08:03:28 PM PDT 24	Jul 04 08:22:04 PM PDT 24	5540179968 ps
T171	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3178863384			Jul 04 07:52:53 PM PDT 24	Jul 04 07:59:03 PM PDT 24	5265365660 ps
T875	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2687056955			Jul 04 07:54:36 PM PDT 24	Jul 04 08:20:56 PM PDT 24	15840781869 ps
T876	/workspace/coverage/default/1.chip_sw_example_manufacturer.4115376650			Jul 04 07:54:31 PM PDT 24	Jul 04 07:57:39 PM PDT 24	2795387200 ps
T709	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3530437892			Jul 04 08:20:30 PM PDT 24	Jul 04 08:26:53 PM PDT 24	3764078272 ps
T331	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2354323425			Jul 04 07:52:10 PM PDT 24	Jul 04 07:56:22 PM PDT 24	2805512499 ps
T877	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1620450755			Jul 04 07:53:46 PM PDT 24	Jul 04 07:57:47 PM PDT 24	3337441068 ps
T209	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1955703747			Jul 04 08:15:58 PM PDT 24	Jul 04 08:35:54 PM PDT 24	8168067678 ps
T350	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2900796208			Jul 04 07:54:41 PM PDT 24	Jul 04 08:14:32 PM PDT 24	13119508195 ps
T878	/workspace/coverage/default/1.chip_sw_uart_smoketest.1170474027			Jul 04 08:01:46 PM PDT 24	Jul 04 08:06:04 PM PDT 24	2738663470 ps
T879	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.172700472			Jul 04 08:14:26 PM PDT 24	Jul 04 08:17:46 PM PDT 24	2763665302 ps
T880	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2835184988			Jul 04 08:01:31 PM PDT 24	Jul 04 08:11:31 PM PDT 24	6715319840 ps
T432	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2967727835			Jul 04 08:02:53 PM PDT 24	Jul 04 08:07:03 PM PDT 24	2683619190 ps
T881	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2181020554			Jul 04 08:02:03 PM PDT 24	Jul 04 08:06:55 PM PDT 24	2775620720 ps
T367	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3258414016			Jul 04 08:14:02 PM PDT 24	Jul 04 08:24:19 PM PDT 24	4840447382 ps
T126	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2933802197			Jul 04 08:04:14 PM PDT 24	Jul 04 08:12:36 PM PDT 24	8310906889 ps
T162	/workspace/coverage/default/4.chip_sw_all_escalation_resets.202509618			Jul 04 08:11:14 PM PDT 24	Jul 04 08:21:07 PM PDT 24	5075787680 ps
T726	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2014650300			Jul 04 08:15:27 PM PDT 24	Jul 04 08:25:44 PM PDT 24	5148306920 ps
T210	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2320302653			Jul 04 07:53:05 PM PDT 24	Jul 04 08:26:56 PM PDT 24	8623729960 ps
T85	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1899868685			Jul 04 08:02:20 PM PDT 24	Jul 04 11:12:54 PM PDT 24	64821613219 ps
T328	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.126059603			Jul 04 07:48:51 PM PDT 24	Jul 04 08:07:08 PM PDT 24	14153278377 ps
T252	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2776219086			Jul 04 07:50:20 PM PDT 24	Jul 04 07:57:43 PM PDT 24	3888027900 ps
T8	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2018533697			Jul 04 07:49:16 PM PDT 24	Jul 04 08:00:51 PM PDT 24	4751165960 ps
T427	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.612202856			Jul 04 07:49:28 PM PDT 24	Jul 04 08:42:31 PM PDT 24	31921388824 ps
T174	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3122676664			Jul 04 07:58:13 PM PDT 24	Jul 04 08:09:44 PM PDT 24	4376001624 ps
T211	/workspace/coverage/default/1.chip_sw_pattgen_ios.4246082036			Jul 04 07:52:05 PM PDT 24	Jul 04 07:55:19 PM PDT 24	2363297240 ps
T395	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1315648178			Jul 04 08:01:33 PM PDT 24	Jul 04 09:50:07 PM PDT 24	23096527848 ps
T82	/workspace/coverage/default/2.chip_jtag_csr_rw.3443940218			Jul 04 08:01:07 PM PDT 24	Jul 04 08:19:37 PM PDT 24	10375699440 ps
T428	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3449233835			Jul 04 07:59:27 PM PDT 24	Jul 04 08:11:26 PM PDT 24	7380747500 ps
T142	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2899291115			Jul 04 07:56:27 PM PDT 24	Jul 04 11:38:13 PM PDT 24	79046619686 ps
T429	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2176348900			Jul 04 08:04:31 PM PDT 24	Jul 04 08:12:25 PM PDT 24	3803732370 ps
T207	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2931052260			Jul 04 07:51:47 PM PDT 24	Jul 04 08:03:09 PM PDT 24	4133620796 ps
T882	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3374252233			Jul 04 08:11:40 PM PDT 24	Jul 04 08:20:25 PM PDT 24	3851909944 ps
T205	/workspace/coverage/default/6.chip_sw_all_escalation_resets.2631759858			Jul 04 08:12:58 PM PDT 24	Jul 04 08:24:58 PM PDT 24	5450425600 ps
T140	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3178426148			Jul 04 07:56:14 PM PDT 24	Jul 04 08:01:43 PM PDT 24	2800550418 ps
T707	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1685350682			Jul 04 08:22:02 PM PDT 24	Jul 04 08:33:38 PM PDT 24	4732002288 ps
T279	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1576440849			Jul 04 07:50:16 PM PDT 24	Jul 04 07:59:46 PM PDT 24	5585899100 ps
T883	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.924002464			Jul 04 07:55:15 PM PDT 24	Jul 04 08:01:19 PM PDT 24	2605654989 ps
T664	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1625267811			Jul 04 08:16:22 PM PDT 24	Jul 04 08:23:05 PM PDT 24	3717152800 ps
T109	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4149128081			Jul 04 08:09:26 PM PDT 24	Jul 04 11:17:19 PM PDT 24	83702523473 ps
T884	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2156673766			Jul 04 07:52:29 PM PDT 24	Jul 04 08:02:32 PM PDT 24	3906246056 ps
T516	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1413019183			Jul 04 07:57:29 PM PDT 24	Jul 04 08:27:18 PM PDT 24	12311433828 ps
T161	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2682178098			Jul 04 07:53:57 PM PDT 24	Jul 04 09:28:23 PM PDT 24	48604160384 ps
T199	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2388012983			Jul 04 08:06:01 PM PDT 24	Jul 04 08:11:44 PM PDT 24	3043808494 ps
T885	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3037891659			Jul 04 07:52:49 PM PDT 24	Jul 04 08:03:35 PM PDT 24	5221358900 ps
T378	/workspace/coverage/default/2.rom_e2e_asm_init_dev.286062269			Jul 04 08:14:19 PM PDT 24	Jul 04 09:07:59 PM PDT 24	15481721413 ps
T886	/workspace/coverage/default/1.chip_sw_example_concurrency.3513875804			Jul 04 07:56:12 PM PDT 24	Jul 04 07:59:52 PM PDT 24	2836000894 ps
T206	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3055896982			Jul 04 07:55:37 PM PDT 24	Jul 04 11:14:57 PM PDT 24	255440219172 ps
T273	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3829778054			Jul 04 08:03:53 PM PDT 24	Jul 04 08:06:27 PM PDT 24	2886415517 ps
T705	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1470382626			Jul 04 07:49:01 PM PDT 24	Jul 04 07:54:15 PM PDT 24	3381730206 ps
T3	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1547586098			Jul 04 07:50:45 PM PDT 24	Jul 04 07:57:42 PM PDT 24	8093016692 ps
T887	/workspace/coverage/default/98.chip_sw_all_escalation_resets.933664117			Jul 04 08:21:05 PM PDT 24	Jul 04 08:34:21 PM PDT 24	5512157566 ps
T711	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1545559697			Jul 04 07:59:20 PM PDT 24	Jul 04 08:23:23 PM PDT 24	8053218226 ps
T25	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3474195328			Jul 04 08:03:03 PM PDT 24	Jul 04 08:18:22 PM PDT 24	7851095152 ps
T253	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3911020149			Jul 04 07:52:02 PM PDT 24	Jul 04 08:38:59 PM PDT 24	31743133056 ps
T175	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3809868700			Jul 04 07:57:03 PM PDT 24	Jul 04 08:10:09 PM PDT 24	9059130376 ps
T309	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.703627839			Jul 04 08:07:07 PM PDT 24	Jul 04 08:23:52 PM PDT 24	5009300719 ps
T310	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2341864509			Jul 04 08:04:10 PM PDT 24	Jul 04 08:11:07 PM PDT 24	3441423492 ps
T280	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2533476201			Jul 04 08:08:18 PM PDT 24	Jul 04 08:17:27 PM PDT 24	4047966220 ps
T154	/workspace/coverage/default/0.chip_plic_all_irqs_10.1696998479			Jul 04 07:48:39 PM PDT 24	Jul 04 07:57:44 PM PDT 24	4565651954 ps
T311	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2996983928			Jul 04 08:15:05 PM PDT 24	Jul 04 09:04:53 PM PDT 24	11999118920 ps
T80	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1841527326			Jul 04 08:06:27 PM PDT 24	Jul 04 08:13:39 PM PDT 24	3136565578 ps
T28	/workspace/coverage/default/2.chip_sw_gpio_smoketest.2369953666			Jul 04 08:09:40 PM PDT 24	Jul 04 08:13:49 PM PDT 24	2837891619 ps
T172	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2131199615			Jul 04 07:52:35 PM PDT 24	Jul 04 09:30:02 PM PDT 24	50685702644 ps
T312	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3862238923			Jul 04 08:15:07 PM PDT 24	Jul 04 08:26:55 PM PDT 24	5192544504 ps
T888	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3334774481			Jul 04 08:06:37 PM PDT 24	Jul 04 09:00:14 PM PDT 24	14952760991 ps
T119	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3980811672			Jul 04 07:50:00 PM PDT 24	Jul 04 08:04:47 PM PDT 24	4420715964 ps
T889	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1558424164			Jul 04 07:49:15 PM PDT 24	Jul 04 08:08:48 PM PDT 24	5115724880 ps
T890	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.332144278			Jul 04 08:09:19 PM PDT 24	Jul 04 08:17:34 PM PDT 24	4766980586 ps
T891	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3003621501			Jul 04 07:50:35 PM PDT 24	Jul 04 08:03:01 PM PDT 24	7107731010 ps
T281	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1943478389			Jul 04 07:55:25 PM PDT 24	Jul 04 08:02:46 PM PDT 24	2986719046 ps
T405	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2881470488			Jul 04 07:59:47 PM PDT 24	Jul 04 08:06:37 PM PDT 24	3928558310 ps
T892	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.585623409			Jul 04 08:05:43 PM PDT 24	Jul 04 08:22:16 PM PDT 24	7838607270 ps
T120	/workspace/coverage/default/0.rom_raw_unlock.3281146949			Jul 04 07:52:47 PM PDT 24	Jul 04 07:56:43 PM PDT 24	5487227125 ps
T157	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3308252707			Jul 04 08:05:24 PM PDT 24	Jul 04 08:35:19 PM PDT 24	15319873640 ps
T893	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1792962223			Jul 04 08:06:45 PM PDT 24	Jul 04 08:13:16 PM PDT 24	4650576442 ps
T894	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2159522516			Jul 04 08:03:52 PM PDT 24	Jul 04 08:25:51 PM PDT 24	8357694120 ps
T29	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.794528546			Jul 04 08:12:57 PM PDT 24	Jul 04 08:22:42 PM PDT 24	4394001408 ps
T369	/workspace/coverage/default/2.chip_sw_flash_crash_alert.65470252			Jul 04 08:09:29 PM PDT 24	Jul 04 08:20:17 PM PDT 24	4155218240 ps
T274	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3854491086			Jul 04 07:53:39 PM PDT 24	Jul 04 08:07:21 PM PDT 24	5249856874 ps
T734	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2539235769			Jul 04 08:21:03 PM PDT 24	Jul 04 08:29:51 PM PDT 24	6261133164 ps
T799	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398462328			Jul 04 08:20:08 PM PDT 24	Jul 04 08:27:10 PM PDT 24	3220908176 ps
T895	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.928120642			Jul 04 07:59:17 PM PDT 24	Jul 04 08:01:44 PM PDT 24	3160023568 ps
T347	/workspace/coverage/default/0.chip_sw_otbn_randomness.2638286472			Jul 04 07:50:47 PM PDT 24	Jul 04 08:09:28 PM PDT 24	6330422952 ps
T896	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1064185541			Jul 04 08:08:32 PM PDT 24	Jul 04 08:28:43 PM PDT 24	6954801261 ps
T897	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2261735459			Jul 04 07:53:35 PM PDT 24	Jul 04 07:56:58 PM PDT 24	2566436348 ps
T898	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1187219115			Jul 04 08:05:57 PM PDT 24	Jul 04 08:15:31 PM PDT 24	5123230254 ps
T179	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1719237108			Jul 04 08:02:38 PM PDT 24	Jul 04 09:25:12 PM PDT 24	44022119550 ps
T124	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2505699337			Jul 04 07:48:28 PM PDT 24	Jul 04 07:58:57 PM PDT 24	6196376041 ps
T7	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1726189381			Jul 04 08:08:06 PM PDT 24	Jul 04 08:14:55 PM PDT 24	7404208480 ps
T720	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2635823533			Jul 04 08:19:44 PM PDT 24	Jul 04 08:25:17 PM PDT 24	3782747788 ps
T121	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3795399071			Jul 04 08:07:36 PM PDT 24	Jul 04 08:18:31 PM PDT 24	4818108456 ps
T899	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3961776405			Jul 04 08:08:21 PM PDT 24	Jul 04 08:20:54 PM PDT 24	3888452046 ps
T900	/workspace/coverage/default/2.chip_sw_edn_kat.497437024			Jul 04 08:06:46 PM PDT 24	Jul 04 08:17:42 PM PDT 24	3022835420 ps
T732	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3956450670			Jul 04 08:14:39 PM PDT 24	Jul 04 08:21:35 PM PDT 24	3969779064 ps
T316	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1375328795			Jul 04 08:17:06 PM PDT 24	Jul 04 08:27:51 PM PDT 24	5340427520 ps
T320	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2489857912			Jul 04 07:57:25 PM PDT 24	Jul 04 08:56:46 PM PDT 24	15126582084 ps
T53	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2368786810			Jul 04 07:50:31 PM PDT 24	Jul 04 07:56:27 PM PDT 24	2888590950 ps
T321	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.926031263			Jul 04 08:05:14 PM PDT 24	Jul 04 08:10:52 PM PDT 24	2224985040 ps
T322	/workspace/coverage/default/97.chip_sw_all_escalation_resets.926368381			Jul 04 08:21:49 PM PDT 24	Jul 04 08:31:35 PM PDT 24	5718970024 ps
T323	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.674532668			Jul 04 08:16:42 PM PDT 24	Jul 04 08:25:01 PM PDT 24	6313530293 ps
T324	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.116795811			Jul 04 08:19:35 PM PDT 24	Jul 04 08:25:40 PM PDT 24	3063201466 ps
T23	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2834418263			Jul 04 07:52:41 PM PDT 24	Jul 04 07:58:08 PM PDT 24	3321054741 ps
T325	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2255101574			Jul 04 08:16:01 PM PDT 24	Jul 04 09:22:45 PM PDT 24	15226126360 ps
T326	/workspace/coverage/default/2.chip_sw_pattgen_ios.141858887			Jul 04 08:03:18 PM PDT 24	Jul 04 08:08:13 PM PDT 24	3257586728 ps
T228	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2401393117			Jul 04 08:08:54 PM PDT 24	Jul 04 08:42:44 PM PDT 24	23782951478 ps
T176	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3539670229			Jul 04 07:59:54 PM PDT 24	Jul 04 08:05:05 PM PDT 24	3477463984 ps
T84	/workspace/coverage/default/0.chip_sw_usbdev_vbus.3168495672			Jul 04 07:46:54 PM PDT 24	Jul 04 07:50:45 PM PDT 24	2757231552 ps
T300	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1617912985			Jul 04 07:58:04 PM PDT 24	Jul 04 09:05:03 PM PDT 24	15483031783 ps
T301	/workspace/coverage/default/1.chip_sival_flash_info_access.325298920			Jul 04 07:54:37 PM PDT 24	Jul 04 07:58:56 PM PDT 24	3252547710 ps
T302	/workspace/coverage/default/2.chip_sw_hmac_oneshot.4290940722			Jul 04 08:05:55 PM PDT 24	Jul 04 08:10:40 PM PDT 24	2928793776 ps
T303	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1133115792			Jul 04 07:58:45 PM PDT 24	Jul 04 09:11:25 PM PDT 24	15646825006 ps
T304	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098423881			Jul 04 08:19:06 PM PDT 24	Jul 04 08:26:54 PM PDT 24	3224617300 ps
T305	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.765668010			Jul 04 07:50:07 PM PDT 24	Jul 04 08:06:33 PM PDT 24	9397245780 ps
T306	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2283016911			Jul 04 08:15:56 PM PDT 24	Jul 04 08:25:45 PM PDT 24	4461955152 ps
T33	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2347675872			Jul 04 07:56:00 PM PDT 24	Jul 04 08:21:41 PM PDT 24	23445122036 ps
T901	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1339179182			Jul 04 07:49:39 PM PDT 24	Jul 04 07:57:30 PM PDT 24	4460608452 ps
T902	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1522242022			Jul 04 07:53:30 PM PDT 24	Jul 04 08:16:34 PM PDT 24	9126174238 ps
T30	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.613846645			Jul 04 07:48:03 PM PDT 24	Jul 04 08:06:39 PM PDT 24	9286122426 ps
T903	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3131695233			Jul 04 08:05:51 PM PDT 24	Jul 04 08:46:31 PM PDT 24	40012628344 ps
T713	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2425800479			Jul 04 08:19:34 PM PDT 24	Jul 04 08:27:08 PM PDT 24	5010306720 ps
T904	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1835552750			Jul 04 08:15:57 PM PDT 24	Jul 04 09:12:29 PM PDT 24	15454758628 ps
T905	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1749460880			Jul 04 07:58:10 PM PDT 24	Jul 04 09:09:56 PM PDT 24	15327468688 ps
T357	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.840835158			Jul 04 07:48:33 PM PDT 24	Jul 04 07:52:05 PM PDT 24	2578536532 ps
T906	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.4288069830			Jul 04 07:57:24 PM PDT 24	Jul 04 08:04:40 PM PDT 24	6018040180 ps
T737	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3593852444			Jul 04 08:15:14 PM PDT 24	Jul 04 08:26:19 PM PDT 24	5109309976 ps
T907	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.697772812			Jul 04 08:08:07 PM PDT 24	Jul 04 09:29:00 PM PDT 24	14756880328 ps
T258	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.197355849			Jul 04 08:15:51 PM PDT 24	Jul 04 08:21:34 PM PDT 24	3691670710 ps
T908	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2085702712			Jul 04 08:01:20 PM PDT 24	Jul 04 08:07:08 PM PDT 24	3714427698 ps
T81	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3090213880			Jul 04 07:48:40 PM PDT 24	Jul 04 08:11:06 PM PDT 24	10402279254 ps
T909	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.375281099			Jul 04 08:13:53 PM PDT 24	Jul 04 08:55:40 PM PDT 24	10844401384 ps
T208	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.282021221			Jul 04 07:53:38 PM PDT 24	Jul 04 08:04:26 PM PDT 24	3571429890 ps
T353	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3781961041			Jul 04 07:49:51 PM PDT 24	Jul 04 08:02:38 PM PDT 24	4445503251 ps
T38	/workspace/coverage/default/2.chip_sw_gpio.277490713			Jul 04 08:04:39 PM PDT 24	Jul 04 08:12:04 PM PDT 24	3706770728 ps
T275	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4043859838			Jul 04 08:10:50 PM PDT 24	Jul 04 08:22:30 PM PDT 24	4773658620 ps
T910	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.446929324			Jul 04 07:47:27 PM PDT 24	Jul 04 07:52:17 PM PDT 24	2526645060 ps
T10	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3998286445			Jul 04 08:02:06 PM PDT 24	Jul 04 08:08:09 PM PDT 24	4302820768 ps