Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3564	1			T437	2		T438	1		T412	31
all_values[1]	3658	1			T76	2		T437	2		T438	3
all_values[2]	3712	1			T76	2		T437	8		T438	3
all_values[3]	3806	1			T76	1		T437	4		T438	3
all_values[4]	3629	1			T76	1		T437	2		T438	4
all_values[5]	3794	1			T76	1		T437	1		T438	3
all_values[6]	3722	1			T76	1		T437	3		T438	1
all_values[7]	3748	1			T76	1		T437	7		T438	4
all_values[8]	3760	1			T76	3		T437	4		T412	31
all_values[9]	3788	1			T437	3		T438	3		T412	25
all_values[10]	3654	1			T76	3		T437	5		T438	1
all_values[11]	3713	1			T76	3		T437	5		T438	1
all_values[12]	3653	1			T76	1		T437	5		T438	3
all_values[13]	3630	1			T76	3		T437	1		T438	2
all_values[14]	3729	1			T76	2		T437	5		T438	2
all_values[15]	3792	1			T76	3		T437	5		T438	3
all_values[16]	3572	1			T76	2		T437	7		T438	3
all_values[17]	3664	1			T76	1		T437	3		T412	34
all_values[18]	3784	1			T76	3		T437	3		T438	3
all_values[19]	3720	1			T76	1		T437	3		T438	1
all_values[20]	3687	1			T76	2		T437	4		T438	2
all_values[21]	3778	1			T76	1		T437	5		T438	2
all_values[22]	3794	1			T76	1		T437	2		T438	1
all_values[23]	3732	1			T76	1		T437	7		T438	3
all_values[24]	3630	1			T76	2		T437	4		T438	1
all_values[25]	3761	1			T437	7		T438	2		T412	17
all_values[26]	3678	1			T76	2		T437	5		T438	1
all_values[27]	3614	1			T76	3		T437	6		T438	1
all_values[28]	3704	1			T437	5		T412	21		T519	22
all_values[29]	3730	1			T76	2		T437	7		T438	3
all_values[30]	3637	1			T76	1		T437	2		T438	1
all_values[31]	3707	1			T76	1		T437	8		T438	1
all_values[32]	3535	1			T76	1		T437	4		T438	3
all_values[33]	3688	1			T437	1		T438	1		T412	25
all_values[34]	3701	1			T76	3		T437	3		T438	1
all_values[35]	3715	1			T76	2		T437	3		T412	20
all_values[36]	3598	1			T76	1		T437	4		T438	4
all_values[37]	3554	1			T76	4		T437	4		T438	1
all_values[38]	3740	1			T76	1		T437	3		T438	3
all_values[39]	3694	1			T76	1		T437	6		T438	2
all_values[40]	3723	1			T76	1		T437	4		T438	1
all_values[41]	3749	1			T437	2		T438	3		T412	26
all_values[42]	3641	1			T437	6		T438	2		T412	22
all_values[43]	3839	1			T76	1		T437	5		T438	3
all_values[44]	3679	1			T76	2		T437	3		T412	27
all_values[45]	3687	1			T76	1		T437	3		T438	2
all_values[46]	3704	1			T76	1		T437	5		T438	2
all_values[47]	3630	1			T76	1		T437	9		T438	4
all_values[48]	3647	1			T437	5		T438	1		T412	20
all_values[49]	3653	1			T76	2		T437	7		T438	4
all_values[50]	3717	1			T76	1		T437	2		T412	27
all_values[51]	3687	1			T76	3		T437	9		T438	1
all_values[52]	3573	1			T437	2		T438	3		T412	19
all_values[53]	3757	1			T76	1		T437	4		T438	4
all_values[54]	3738	1			T76	2		T437	2		T438	2
all_values[55]	3682	1			T76	1		T437	4		T438	4
all_values[56]	3923	1			T76	2		T437	3		T438	4
all_values[57]	3692	1			T437	4		T438	5		T412	16
all_values[58]	3588	1			T437	4		T438	3		T412	25
all_values[59]	3768	1			T437	3		T438	3		T412	21
all_values[60]	3607	1			T76	1		T437	9		T438	4
all_values[61]	3686	1			T76	3		T437	1		T438	2
all_values[62]	3660	1			T76	2		T437	5		T438	3
all_values[63]	3588	1			T437	4		T438	3		T412	25