Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1037308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35048333

1

T4

57485

T5

7127

T6

20379

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24968614	1			T4	50938		T5	3136		T6	12877
values[0x0]	10078766	1			T4	6547		T5	3991		T6	7502
values[0x1]	1038261	1			T4	319		T5	314		T6	2559

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36076892

1

T4

57804

T5

7441

T6

22938

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18029277	1			T4	28903		T5	3721		T6	11469
valid_sources[0x01]	18028344	1			T4	28901		T5	3720		T6	11469
valid_sources[0x02]	269	1			T8	1		T67	2		T121	4
valid_sources[0x03]	319	1			T67	1		T103	2		T42	33
valid_sources[0x04]	281	1			T8	1		T67	2		T42	29
valid_sources[0x05]	327	1			T8	1		T103	2		T121	1
valid_sources[0x06]	293	1			T42	24		T44	59		T46	30
valid_sources[0x07]	348	1			T42	42		T44	62		T46	68
valid_sources[0x08]	331	1			T42	40		T43	16		T44	55
valid_sources[0x09]	349	1			T42	36		T43	16		T44	58
valid_sources[0x0a]	334	1			T67	1		T121	2		T42	47
valid_sources[0x0b]	349	1			T8	1		T42	24		T44	62
valid_sources[0x0c]	238	1			T42	32		T44	43		T46	6
valid_sources[0x0d]	325	1			T8	1		T103	3		T42	33
valid_sources[0x0e]	376	1			T8	1		T103	3		T42	33
valid_sources[0x0f]	278	1			T8	1		T121	5		T42	33
valid_sources[0x10]	2728	1			T8	1		T67	3		T103	1
valid_sources[0x11]	312	1			T67	3		T42	30		T44	57
valid_sources[0x12]	294	1			T8	1		T67	1		T103	1
valid_sources[0x13]	376	1			T8	1		T103	2		T121	1
valid_sources[0x14]	309	1			T67	2		T42	30		T44	61
valid_sources[0x15]	307	1			T42	49		T43	20		T44	43
valid_sources[0x16]	319	1			T8	1		T42	47		T44	52
valid_sources[0x17]	397	1			T8	1		T103	1		T42	35
valid_sources[0x18]	286	1			T8	2		T103	1		T121	2
valid_sources[0x19]	320	1			T103	3		T121	1		T42	56
valid_sources[0x1a]	341	1			T121	2		T42	37		T43	16
valid_sources[0x1b]	289	1			T42	33		T44	61		T46	41
valid_sources[0x1c]	354	1			T8	1		T42	53		T43	16
valid_sources[0x1d]	485	1			T103	1		T42	29		T44	66
valid_sources[0x1e]	253	1			T121	2		T42	51		T44	58
valid_sources[0x1f]	3409	1			T42	37		T43	3059		T44	76
valid_sources[0x20]	326	1			T67	1		T103	1		T42	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24968614

1

T4

50938

T5

3136

T6

12877

values[0x0]

all_enables

biggest_size

10074356

1

T4

6547

T5

3991

T6

7502

values[0x1]

all_enables

biggest_size

5363

1

T66

20

T8

23

T67

22