Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	84.48			84.48
tb.dut.top_earlgrey.u_i2c1	84.57			84.57
tb.dut.top_earlgrey.u_i2c2	84.57			84.57

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.48			84.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.48			84.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	352	298	84.66
Total Bits 0->1	176	149	84.66
Total Bits 1->0	176	149	84.66

Ports	54	40	74.07
Port Bits	352	298	84.66
Port Bits 0->1	176	149	84.66
Port Bits 1->0	176	149	84.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	INPUT
tl_o.a_ready	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T186,T187,T188	Yes	T186,T187,T112	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T184,*T189,T190	Yes	T186,T187,T112	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T186,T187,T188	Yes	T186,T187,T112	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T103,*T186,*T187	Yes	T103,T186,T187	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T184,T189,T190	Yes	T186,T187,T112	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T186,*T187,*T188	Yes	T186,T187,T188	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	OUTPUT
cio_scl_i	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T187,T188,T191	Yes	T187,T188,T191	OUTPUT
cio_sda_i	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T187,T188,T191	Yes	T187,T188,T191	OUTPUT
intr_rx_threshold_o	Yes	Yes	T187,T188,T191	Yes	T187,T188,T191	OUTPUT
intr_acq_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_rx_overflow_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_controller_halt_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_scl_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_unstable_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_cmd_complete_o	Yes	Yes	T186,T187,T188	Yes	T186,T187,T188	OUTPUT
intr_tx_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_tx_threshold_o	Yes	Yes	T192,T193,T103	Yes	T192,T193,T103	OUTPUT
intr_acq_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_unexp_stop_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_host_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	348	294	84.48
Total Bits 0->1	174	147	84.48
Total Bits 1->0	174	147	84.48

Ports	54	40	74.07
Port Bits	348	294	84.48
Port Bits 0->1	174	147	84.48
Port Bits 1->0	174	147	84.48

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T188,T184,T195	Yes	T188,T184,T195	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T188,T184,T195	Yes	T188,T184,T195	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T112,T188,T113	Yes	T112,T188,T113	INPUT
tl_o.a_ready	Yes	Yes	T112,T188,T113	Yes	T112,T188,T113	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T188,T195,T192	Yes	T188,T195,T192	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T188,T184,T195	Yes	T112,T188,T113	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T184,*T189,T190	Yes	T112,T188,T113	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T188,T184,T195	Yes	T112,T188,T113	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T103,*T188,*T184	Yes	T103,T112,T188	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T184,T189,T190	Yes	T112,T188,T113	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T188,*T184,*T195	Yes	T188,T184,T195	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T112,T188,T113	Yes	T112,T188,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	OUTPUT
cio_scl_i	Yes	Yes	T188,T195,T196	Yes	T188,T195,T196	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T188,T196,T197	Yes	T188,T196,T197	OUTPUT
cio_sda_i	Yes	Yes	T188,T195,T196	Yes	T188,T195,T196	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T188,T195,T196	Yes	T188,T195,T196	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T188,T192,T196	Yes	T188,T192,T196	OUTPUT
intr_rx_threshold_o	Yes	Yes	T188,T192,T196	Yes	T188,T192,T196	OUTPUT
intr_acq_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_rx_overflow_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_controller_halt_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_scl_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_unstable_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_cmd_complete_o	Yes	Yes	T188,T195,T192	Yes	T188,T195,T192	OUTPUT
intr_tx_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_tx_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_acq_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_unexp_stop_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_host_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	296	84.57
Total Bits 0->1	175	148	84.57
Total Bits 1->0	175	148	84.57

Ports	54	40	74.07
Port Bits	350	296	84.57
Port Bits 0->1	175	148	84.57
Port Bits 1->0	175	148	84.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T191,T184,T192	Yes	T191,T184,T192	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T191,T184,T192	Yes	T191,T184,T192	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T112,T191,T113	Yes	T112,T191,T113	INPUT
tl_o.a_ready	Yes	Yes	T112,T191,T113	Yes	T112,T191,T113	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T191,T192,T198	Yes	T191,T192,T198	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T191,T184,T189	Yes	T112,T191,T113	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T184,*T189,T190	Yes	T112,T191,T113	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T191,T184,T189	Yes	T112,T191,T113	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T103,*T191,*T184	Yes	T103,T112,T191	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T184,T189,T190	Yes	T112,T191,T113	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T191,*T184,*T192	Yes	T191,T184,T192	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T112,T191,T113	Yes	T112,T191,T113	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	OUTPUT
cio_scl_i	Yes	Yes	T191,T198,T199	Yes	T191,T198,T199	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T191,T198,T199	Yes	T191,T198,T199	OUTPUT
cio_sda_i	Yes	Yes	T191,T198,T199	Yes	T191,T198,T199	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T191,T198,T199	Yes	T191,T198,T199	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T191,T192,T198	Yes	T191,T192,T198	OUTPUT
intr_rx_threshold_o	Yes	Yes	T191,T192,T198	Yes	T191,T192,T198	OUTPUT
intr_acq_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_rx_overflow_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_controller_halt_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_scl_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_unstable_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_cmd_complete_o	Yes	Yes	T191,T192,T198	Yes	T191,T192,T198	OUTPUT
intr_tx_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_tx_threshold_o	Yes	Yes	T192,T193,T103	Yes	T192,T193,T103	OUTPUT
intr_acq_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_unexp_stop_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_host_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	296	84.57
Total Bits 0->1	175	148	84.57
Total Bits 1->0	175	148	84.57

Ports	54	40	74.07
Port Bits	350	296	84.57
Port Bits 0->1	175	148	84.57
Port Bits 1->0	175	148	84.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	INPUT
tl_o.a_ready	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T186,T187,T200	Yes	T186,T187,T112	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T184,*T189,T190	Yes	T186,T187,T112	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T186,T187,T200	Yes	T186,T187,T112	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T103,*T186,*T187	Yes	T103,T186,T187	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T184,T189,T190	Yes	T186,T187,T112	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T186,*T187,*T200	Yes	T186,T187,T200	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T186,T187,T112	Yes	T186,T187,T112	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	OUTPUT
cio_scl_i	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T187,T200,T201	Yes	T187,T200,T201	OUTPUT
cio_sda_i	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T187,T200,T192	Yes	T187,T200,T192	OUTPUT
intr_rx_threshold_o	Yes	Yes	T187,T200,T192	Yes	T187,T200,T192	OUTPUT
intr_acq_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_rx_overflow_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_controller_halt_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_scl_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_interference_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_sda_unstable_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_cmd_complete_o	Yes	Yes	T186,T187,T200	Yes	T186,T187,T200	OUTPUT
intr_tx_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_tx_threshold_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_acq_stretch_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_unexp_stop_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT
intr_host_timeout_o	Yes	Yes	T192,T193,T194	Yes	T192,T193,T194	OUTPUT

*Tests covering at least one bit in the range