Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	57476274	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	57476274	0	0
T4	489146	68956	0	0
T5	138290	18644	0	0
T6	208516	39499	0	0
T18	588760	55009	0	0
T45	814498	116392	0	0
T59	259452	18270	0	0
T75	157549	21269	0	0
T115	270030	35491	0	0
T116	247512	24070	0	0
T125	378960	46838	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	44814640	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	44814640	0	0
T4	489146	62045	0	0
T5	138290	13510	0	0
T6	208516	29489	0	0
T18	588760	41729	0	0
T45	814498	108086	0	0
T59	259452	14285	0	0
T75	157549	16189	0	0
T115	270030	25890	0	0
T116	247512	17148	0	0
T125	378960	37051	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	42381096	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	42381096	0	0
T4	489146	58220	0	0
T5	138290	7719	0	0
T6	208516	23486	0	0
T18	588760	26045	0	0
T45	814498	100814	0	0
T59	259452	10826	0	0
T75	157549	9662	0	0
T115	270030	18444	0	0
T116	247512	16759	0	0
T125	378960	45003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	36150395	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	36150395	0	0
T4	489146	57804	0	0
T5	138290	7441	0	0
T6	208516	22938	0	0
T18	588760	25276	0	0
T45	814498	100337	0	0
T59	259452	10574	0	0
T75	157549	9394	0	0
T115	270030	18061	0	0
T116	247512	16142	0	0
T125	378960	42395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	63054	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	63054	0	0
T4	489146	39	0	0
T5	138290	26	0	0
T6	208516	15	0	0
T18	588760	181	0	0
T45	814498	75	0	0
T59	259452	29	0	0
T75	157549	26	0	0
T115	270030	151	0	0
T116	247512	299	0	0
T125	378960	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	63054	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	63054	0	0
T4	489146	39	0	0
T5	138290	26	0	0
T6	208516	15	0	0
T18	588760	181	0	0
T45	814498	75	0	0
T59	259452	29	0	0
T75	157549	26	0	0
T115	270030	151	0	0
T116	247512	299	0	0
T125	378960	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	50375	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	50375	0	0
T4	489146	37	0	0
T5	138290	23	0	0
T6	208516	12	0	0
T18	588760	176	0	0
T45	814498	73	0	0
T59	259452	25	0	0
T75	157549	23	0	0
T115	270030	95	0	0
T116	247512	175	0	0
T125	378960	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	50375	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	50375	0	0
T4	489146	37	0	0
T5	138290	23	0	0
T6	208516	12	0	0
T18	588760	176	0	0
T45	814498	73	0	0
T59	259452	25	0	0
T75	157549	23	0	0
T115	270030	95	0	0
T116	247512	175	0	0
T125	378960	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	12679	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	12679	0	0
T4	489146	2	0	0
T5	138290	3	0	0
T6	208516	3	0	0
T18	588760	5	0	0
T45	814498	2	0	0
T59	259452	4	0	0
T75	157549	3	0	0
T115	270030	56	0	0
T116	247512	124	0	0
T125	378960	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509220035	12679	0	0
DepthKnown_A	509220035	509112780	0	0
RvalidKnown_A	509220035	509112780	0	0
WreadyKnown_A	509220035	509112780	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	12679	0	0
T4	489146	2	0	0
T5	138290	3	0	0
T6	208516	3	0	0
T18	588760	5	0	0
T45	814498	2	0	0
T59	259452	4	0	0
T75	157549	3	0	0
T115	270030	56	0	0
T116	247512	124	0	0
T125	378960	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	509112780	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0