Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_usbdev	82.35			82.35

---

Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.35			82.35

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	77	60	77.92
Total Bits	408	336	82.35
Total Bits 0->1	204	168	82.35
Total Bits 1->0	204	168	82.35

Ports	77	60	77.92
Port Bits	408	336	82.35
Port Bits 0->1	204	168	82.35
Port Bits 1->0	204	168	82.35

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T18,*T1,*T2	Yes	T18,T1,T2	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[11:2]	Yes	Yes	*T18,*T124,T31	Yes	T18,T124,T31	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T18,*T1,*T2	Yes	T18,T1,T2	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T18,*T1,*T2	Yes	T18,T1,T2	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T18,*T2,*T3	Yes	T18,T2,T3	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T18,T124,T31	Yes	T18,T124,T31	INPUT
tl_i.a_valid	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	INPUT
tl_o.a_ready	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T31,T145	Yes	T18,T124,T31	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,*T124,T31	Yes	T18,T31,T145	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T18,T1,T3	Yes	T18,T1,T2	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T1,T2	Yes	T18,T1,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T18,*T3,*T31	Yes	T18,T2,T3	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T18,T1,T3	Yes	T18,T1,T2	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T1,*T2	Yes	T18,T1,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T1,T2	Yes	T18,T1,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T115,T104,T105	Yes	T115,T104,T105	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T115,T104,T105	Yes	T115,T104,T105	OUTPUT
cio_usb_dp_i	Yes	Yes	T124,T31,T22	Yes	T31,T35,T36	INPUT
cio_usb_dn_i	Yes	Yes	T31,T35,T36	Yes	T31,T23,T35	INPUT
usb_rx_d_i	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T3,T31	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
cio_usb_dn_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
usb_tx_se0_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T3,T31	OUTPUT
cio_sense_i	Yes	Yes	T120,T42,T43	Yes	T124,T31,T35	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T3,T31	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T118,T119,T120	Yes	T118,T119,T120	OUTPUT
usb_rx_enable_o	Yes	Yes	T120	Yes	T31,T35,T36	OUTPUT
usb_tx_use_d_se0_o	No	No		No		OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T118	Yes	T118	INPUT
usb_aon_sense_lost_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_ref_val_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
usb_ref_pulse_o	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_pkt_sent_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_powered_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_disconnected_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_host_lost_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_link_reset_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_link_suspend_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_link_resume_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_av_out_empty_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_full_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_av_overflow_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_link_in_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_link_out_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_frame_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range