Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	89.47			89.47
tb.dut.top_earlgrey.u_uart1	89.54			89.54
tb.dut.top_earlgrey.u_uart2	89.54			89.54
tb.dut.top_earlgrey.u_uart3	89.61			89.61

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47			89.47

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	276	89.61
Total Bits 0->1	154	138	89.61
Total Bits 1->0	154	138	89.61

Ports	40	32	80.00
Port Bits	308	276	89.61
Port Bits 0->1	154	138	89.61
Port Bits 1->0	154	138	89.61

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T59,T96	Yes	T18,T59,T96	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T59,T96	Yes	T18,T59,T96	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T18,T59,T96	Yes	T18,T59,T96	INPUT
tl_o.a_ready	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T18,T20,T56	Yes	T18,T96,T19	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T18,*T96,*T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T18,T20,T56	Yes	T18,T96,T19	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T96,*T19	Yes	T18,T96,T19	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	OUTPUT
cio_rx_i	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T96,T19,T20	Yes	T96,T19,T20	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T96,T19	Yes	T18,T96,T19	OUTPUT
intr_tx_empty_o	Yes	Yes	T96,T19,T308	Yes	T96,T19,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T96,T19,T308	Yes	T96,T19,T308	OUTPUT
intr_tx_done_o	Yes	Yes	T96,T19,T308	Yes	T96,T19,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T96,T19,T308	Yes	T96,T19,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_break_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_timeout_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	272	89.47
Total Bits 0->1	152	136	89.47
Total Bits 1->0	152	136	89.47

Ports	40	32	80.00
Port Bits	304	272	89.47
Port Bits 0->1	152	136	89.47
Port Bits 1->0	152	136	89.47

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T59,T20	Yes	T18,T59,T20	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T59,T20	Yes	T18,T59,T20	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T18,T59,T20	Yes	T18,T59,T20	INPUT
tl_o.a_ready	Yes	Yes	T18,T20,T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T20,T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,T20,T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T18,T20,T56	Yes	T18,T20,T58	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T20,T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T18,*T20,*T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T18,T20,T56	Yes	T18,T20,T58	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T20,*T58	Yes	T18,T20,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T20,T58	Yes	T18,T20,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	OUTPUT
cio_rx_i	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T20,T58,T56	Yes	T20,T58,T56	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T312,T313	Yes	T18,T312,T313	OUTPUT
intr_tx_empty_o	Yes	Yes	T312,T313,T342	Yes	T312,T313,T342	OUTPUT
intr_rx_watermark_o	Yes	Yes	T312,T313,T342	Yes	T312,T313,T342	OUTPUT
intr_tx_done_o	Yes	Yes	T312,T313,T342	Yes	T312,T313,T342	OUTPUT
intr_rx_overflow_o	Yes	Yes	T312,T313,T342	Yes	T312,T313,T342	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_break_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_timeout_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	INPUT
tl_o.a_ready	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T189,*T343,*T344	Yes	T19,T308,T309	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T19,*T308,*T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T189,T343,T344	Yes	T19,T308,T309	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T19,*T308,*T309	Yes	T19,T308,T309	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	OUTPUT
cio_rx_i	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	INPUT
cio_tx_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
intr_tx_done_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
intr_rx_overflow_o	Yes	Yes	T19,T308,T309	Yes	T19,T308,T309	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_break_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_timeout_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_o.a_ready	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T189,*T343,*T344	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T189,T343,T344	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	OUTPUT
cio_rx_i	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
cio_tx_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_tx_empty_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_rx_watermark_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_tx_done_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_rx_overflow_o	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_break_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_timeout_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	276	89.61
Total Bits 0->1	154	138	89.61
Total Bits 1->0	154	138	89.61

Ports	40	32	80.00
Port Bits	308	276	89.61
Port Bits 0->1	154	138	89.61
Port Bits 1->0	154	138	89.61

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T28,T112,T30	Yes	T28,T112,T30	INPUT
tl_o.a_ready	Yes	Yes	T28,T112,T30	Yes	T28,T112,T30	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T28,T30,T296	Yes	T28,T112,T30	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T189,*T343,*T344	Yes	T28,T112,T30	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T30,T296	Yes	T28,T112,T30	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T28,*T30,*T296	Yes	T28,T30,T296	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T189,T343,T344	Yes	T28,T112,T30	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T30,*T296	Yes	T28,T30,T296	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T28,T112,T30	Yes	T28,T112,T30	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T105,T106,T112	Yes	T105,T106,T112	OUTPUT
cio_rx_i	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	INPUT
cio_tx_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T30,T296	Yes	T28,T30,T296	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_break_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_timeout_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T146,T147,T148	Yes	T146,T147,T148	OUTPUT

*Tests covering at least one bit in the range