Unified Coverage Report :: Module :: sensor_ctrl

Module : sensor_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.65	93.69	90.00	79.58		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon	92.65	93.69	90.00	79.58		100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.65	93.69	90.00	79.58		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	93.47	86.01	79.58		95.77	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_sync_assign[0].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[10].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[1].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[2].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[3].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[4].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[5].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[6].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[7].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[8].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[9].u_alert_in_buf	100.00	100.00
u_alert_n_sync	100.00	100.00				100.00
u_alert_p_sync	100.00	100.00				100.00
u_init_chg	100.00	100.00	100.00			100.00
u_init_intr	100.00	100.00	100.00			100.00	100.00
u_io_intr	100.00	100.00	100.00			100.00	100.00
u_io_status_chg	100.00	100.00				100.00
u_prim_sec_anchor_buf	100.00	100.00
u_reg	93.39	92.96	85.17			95.45	100.00
u_wake_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
TOTAL		111	104	93.69
ALWAYS	186	0	0
ALWAYS	186	2	2	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	244	0	0
ALWAYS	244	3	3	100.00
ALWAYS	252	0	0
ALWAYS	252	3	3	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	330	3	3	100.00
ALWAYS	341	3	3	100.00
ALWAYS	356	11	11	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	391	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
186	1	1
187	1	1
211	11	11
214	11	11
217	11	11
222	11	11
225	4	11
228	11	11
234	1	1
244	1	1
245	1	1
246	1	1
252	1	1
253	1	1
254	1	1
261	1	1
263	1	1
314	1	1
330	1	1
331	1	1
333	1	1
341	1	1
342	1	1
344	1	1
356	1	1
357	1	1
358	1	1
359	1	1
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
365	1	1
366	1	1
			MISSING_ELSE
368	1	1
369	1	1
			MISSING_ELSE
376	4	4
377	4	4
378	4	4
379	4	4
391		unreachable

---

Cond Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Conditions	100	90	90.00
Logical	100	90	90.00
Non-Logical	0	0
Event	0	0

 LINE       187
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T74
0	1	Not Covered
1	0	Covered	T406,T407,T408

 LINE       214
 EXPRESSION (alert_en_buf[0] && event_vld[0] && ((!reg2hw.fatal_alert_en[0])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T90,T91,T87
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T90,T91,T93
1	1	1	Covered	T1,T2,T74

 LINE       214
 EXPRESSION (alert_en_buf[1] && event_vld[1] && ((!reg2hw.fatal_alert_en[1])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T88,T89

 LINE       214
 EXPRESSION (alert_en_buf[2] && event_vld[2] && ((!reg2hw.fatal_alert_en[2])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T90,T91,T92
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T90,T91,T92
1	1	1	Covered	T90,T91,T92

 LINE       214
 EXPRESSION (alert_en_buf[3] && event_vld[3] && ((!reg2hw.fatal_alert_en[3])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T88,T89

 LINE       214
 EXPRESSION (alert_en_buf[4] && event_vld[4] && ((!reg2hw.fatal_alert_en[4])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T90,T91,T87
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T90,T91,T93
1	1	1	Covered	T90,T91,T87

 LINE       214
 EXPRESSION (alert_en_buf[5] && event_vld[5] && ((!reg2hw.fatal_alert_en[5])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T88,T89

 LINE       214
 EXPRESSION (alert_en_buf[6] && event_vld[6] && ((!reg2hw.fatal_alert_en[6])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T92,T87,T88
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T92
1	1	1	Covered	T92,T87,T88

 LINE       214
 EXPRESSION (alert_en_buf[7] && event_vld[7] && ((!reg2hw.fatal_alert_en[7])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T86,T88

 LINE       214
 EXPRESSION (alert_en_buf[8] && event_vld[8] && ((!reg2hw.fatal_alert_en[8])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T86,T88

 LINE       214
 EXPRESSION (alert_en_buf[9] && event_vld[9] && ((!reg2hw.fatal_alert_en[9])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T88,T89

 LINE       214
 EXPRESSION (alert_en_buf[10] && event_vld[10] && ((!reg2hw.fatal_alert_en[10])))
             --------1-------    ------2------    ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T87,T88,T89
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T87,T88,T89

 LINE       217
 EXPRESSION (alert_en_buf[0] && event_vld[0] && reg2hw.fatal_alert_en[0])
             -------1-------    ------2-----    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T90,T91,T93
1	0	1	Covered	T103
1	1	0	Covered	T1,T2,T74
1	1	1	Covered	T90,T91,T93

 LINE       228
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T74
1	0	Covered	T1,T2,T74
1	1	Covered	T1,T2,T74

 LINE       228
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       228
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T90,T91,T92
1	0	Covered	T90,T91,T92
1	1	Covered	T90,T91,T92

 LINE       228
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       228
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T90,T91,T87
1	0	Covered	T90,T91,T87
1	1	Covered	T90,T91,T87

 LINE       228
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       228
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T92,T87,T88
1	0	Covered	T92,T87,T88
1	1	Covered	T92,T87,T88

 LINE       228
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T86,T88
1	0	Covered	T87,T86,T88
1	1	Covered	T87,T86,T88

 LINE       228
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T86,T88
1	0	Covered	T87,T86,T88
1	1	Covered	T87,T86,T88

 LINE       228
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       228
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       245
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T74
1	1	Covered	T1,T2,T74

 LINE       246
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T406,T407,T408
1	0	Covered	T1,T2,T74
1	1	Covered	T1,T2,T74

 LINE       261
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T112,T113,T114
1	1	Covered	T112,T113,T114

 LINE       263
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T112,T113,T114
1	1	Covered	T112,T113,T114

 LINE       314
 EXPRESSION (((|(async_alert_event_p & alert_en_buf))) | ((~&(async_alert_event_n | (~alert_en_buf)))) | ((|reg2hw.recov_alert)))
             --------------------1--------------------   ----------------------2----------------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T1,T2,T74
0	1	0	Not Covered
1	0	0	Covered	T406,T407,T408

---

Toggle Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Totals	148	104	70.27
Total Bits	568	452	79.58
Total Bits 0->1	284	226	79.58
Total Bits 1->0	284	226	79.58

Ports	148	104	70.27
Port Bits	568	452	79.58
Port Bits 0->1	284	226	79.58
Port Bits 1->0	284	226	79.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T66,*T8,*T67	Yes	T66,T8,T67	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T20,T56,T1	Yes	T20,T56,T1	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T20,T56,T1	Yes	T20,T56,T1	OUTPUT
tl_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:3]	Yes	Yes	*T42,*T43,*T44	Yes	T42,T43,T44	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T18,T45	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T103,*T4,*T18	Yes	T103,T4,T5	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T18,*T45	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ast_alert_i.alerts[0].n	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	INPUT
ast_alert_i.alerts[0].p	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	INPUT
ast_alert_i.alerts[1].n	No	Yes	T87,T88,T89	No		INPUT
ast_alert_i.alerts[1].p	No	No		Yes	T87,T88,T89	INPUT
ast_alert_i.alerts[2].n	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	INPUT
ast_alert_i.alerts[2].p	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	INPUT
ast_alert_i.alerts[3].n	No	Yes	T87,T88,T89	No		INPUT
ast_alert_i.alerts[3].p	No	No		Yes	T87,T88,T89	INPUT
ast_alert_i.alerts[4].n	Yes	Yes	T90,T91,T87	Yes	T90,T91,T93	INPUT
ast_alert_i.alerts[4].p	Yes	Yes	T90,T91,T93	Yes	T90,T91,T87	INPUT
ast_alert_i.alerts[5].n	No	Yes	T87,T88,T89	No		INPUT
ast_alert_i.alerts[5].p	No	No		Yes	T87,T88,T89	INPUT
ast_alert_i.alerts[6].n	Yes	Yes	T92,T87,T88	Yes	T92	INPUT
ast_alert_i.alerts[6].p	Yes	Yes	T92	Yes	T92,T87,T88	INPUT
ast_alert_i.alerts[7].n	Yes	Yes	T87,T86,T88	Yes	T86	INPUT
ast_alert_i.alerts[7].p	Yes	Yes	T86	Yes	T87,T86,T88	INPUT
ast_alert_i.alerts[8].n	Yes	Yes	T87,T86,T88	Yes	T86	INPUT
ast_alert_i.alerts[8].p	Yes	Yes	T86	Yes	T87,T86,T88	INPUT
ast_alert_i.alerts[9].n	No	Yes	T87,T88,T89	No		INPUT
ast_alert_i.alerts[9].p	No	No		Yes	T87,T88,T89	INPUT
ast_alert_i.alerts[10].n	No	Yes	T87,T88,T89	No		INPUT
ast_alert_i.alerts[10].p	No	No		Yes	T87,T88,T89	INPUT
ast_alert_o.alerts_trig[0].n	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	OUTPUT
ast_alert_o.alerts_trig[0].p	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	OUTPUT
ast_alert_o.alerts_trig[1].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[1].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[2].n	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	OUTPUT
ast_alert_o.alerts_trig[2].p	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	OUTPUT
ast_alert_o.alerts_trig[3].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[3].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[4].n	Yes	Yes	T90,T91,T87	Yes	T90,T91,T87	OUTPUT
ast_alert_o.alerts_trig[4].p	Yes	Yes	T90,T91,T87	Yes	T90,T91,T87	OUTPUT
ast_alert_o.alerts_trig[5].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[5].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[6].n	Yes	Yes	T92,T87,T88	Yes	T92,T87,T88	OUTPUT
ast_alert_o.alerts_trig[6].p	Yes	Yes	T92,T87,T88	Yes	T92,T87,T88	OUTPUT
ast_alert_o.alerts_trig[7].n	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_trig[7].p	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_trig[8].n	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_trig[8].p	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_trig[9].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[9].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[10].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_trig[10].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[0].n	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	OUTPUT
ast_alert_o.alerts_ack[0].p	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	OUTPUT
ast_alert_o.alerts_ack[1].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[1].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[2].n	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	OUTPUT
ast_alert_o.alerts_ack[2].p	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	OUTPUT
ast_alert_o.alerts_ack[3].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[3].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[4].n	Yes	Yes	T90,T91,T87	Yes	T90,T91,T87	OUTPUT
ast_alert_o.alerts_ack[4].p	Yes	Yes	T90,T91,T87	Yes	T90,T91,T87	OUTPUT
ast_alert_o.alerts_ack[5].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[5].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[6].n	Yes	Yes	T92,T87,T88	Yes	T92,T87,T88	OUTPUT
ast_alert_o.alerts_ack[6].p	Yes	Yes	T92,T87,T88	Yes	T92,T87,T88	OUTPUT
ast_alert_o.alerts_ack[7].n	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_ack[7].p	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_ack[8].n	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_ack[8].p	Yes	Yes	T87,T86,T88	Yes	T87,T86,T88	OUTPUT
ast_alert_o.alerts_ack[9].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[9].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[10].n	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_alert_o.alerts_ack[10].p	Yes	Yes	T87,T88,T89	Yes	T87,T88,T89	OUTPUT
ast_status_i.io_pok[1:0]	Yes	Yes	T70,T71,T72	Yes	T4,T5,T6	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T18,T45	INPUT
cio_ast_debug_out_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ast_debug_out_en_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_io_status_change_o	Yes	Yes	T109,T71,T110	Yes	T109,T71,T110	OUTPUT
intr_init_status_change_o	Yes	Yes	T109,T110,T111	Yes	T109,T110,T111	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T105	Yes	T1,T2,T105	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T105,T106,T409	Yes	T105,T106,T409	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T105,T106,T123	Yes	T105,T106,T123	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T105	Yes	T1,T2,T105	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T105,T106,T409	Yes	T105,T106,T409	OUTPUT
wkup_req_o	Yes	Yes	T1,T2,T74	Yes	T1,T2,T74	OUTPUT
manual_pad_attr_o[0].invert	No	No		No		OUTPUT
manual_pad_attr_o[0].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[0].pull_en	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[0].pull_select	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[0].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[0].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[0].od_en	No	No		No		OUTPUT
manual_pad_attr_o[0].input_disable	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[0].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[1].invert	No	No		No		OUTPUT
manual_pad_attr_o[1].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[1].pull_en	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[1].pull_select	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[1].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[1].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[1].od_en	No	No		No		OUTPUT
manual_pad_attr_o[1].input_disable	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[1].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[2].invert	No	No		No		OUTPUT
manual_pad_attr_o[2].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[2].pull_en	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[2].pull_select	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[2].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[2].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[2].od_en	No	No		No		OUTPUT
manual_pad_attr_o[2].input_disable	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[2].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[3].invert	No	No		No		OUTPUT
manual_pad_attr_o[3].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[3].pull_en	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[3].pull_select	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[3].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[3].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[3].od_en	No	No		No		OUTPUT
manual_pad_attr_o[3].input_disable	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
manual_pad_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[3].drive_strength[3:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	330	2	2	100.00
IF	341	2	2	100.00
IF	356	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	341	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	356	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : sensor_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmRegWeOnehotCheck_A	126182683	6	0	0
NumAlertsMatch_A	1013	1013	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126182683	6	0	0
T65	132729	0	0	0
T102	67435	0	0	0
T117	153902	0	0	0
T154	22367	0	0	0
T220	120264	0	0	0
T226	69800	0	0	0
T236	147286	0	0	0
T312	266837	0	0	0
T377	0	1	0	0
T409	30620	1	0	0
T410	0	1	0	0
T411	0	1	0	0
T412	0	1	0	0
T413	0	1	0	0
T414	31195	0	0	0

NumAlertsMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0