Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.96 84.96

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 84.96 84.96


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.96 84.96


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.96 84.96


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.56 90.68 87.00 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 311 56.55
Total Bits 6824 5798 84.96
Total Bits 0->1 3412 2899 84.96
Total Bits 1->0 3412 2899 84.96

Ports 550 311 56.55
Port Bits 6824 5798 84.96
Port Bits 0->1 3412 2899 84.96
Port Bits 1->0 3412 2899 84.96

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T115,T210,T211 Yes T115,T210,T211 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T115,*T116,*T210 Yes T115,T116,T210 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T66,T8,T67 Yes T66,T8,T67 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T43,T44,T212 Yes T43,T44,T212 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T115,T116,T213 Yes T115,T116,T213 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T61,T63,T64 Yes T61,T63,T64 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T4,*T18,*T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T61,T63,T64 Yes T61,T63,T64 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T61,T63,T64 Yes T61,T63,T64 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T61,T64,T66 Yes T61,T64,T66 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T61,*T63,*T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T61,T63,T64 Yes T61,T63,T64 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0] Yes Yes *T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0] Yes Yes *T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[7:0] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_data[8] No No No OUTPUT
tl_rv_dm__regs_o.a_data[15:9] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_data[17:16] No No No OUTPUT
tl_rv_dm__regs_o.a_data[27:18] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_data[28] No No No OUTPUT
tl_rv_dm__regs_o.a_data[31:29] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[0] Yes Yes *T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_source[5:1] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[0] No No No OUTPUT
tl_rv_dm__regs_o.a_size[1] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_opcode[2] Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T8 Yes T8 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[0] No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[2:1] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_user.data_intg[3] No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[5:4] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[0] Yes Yes *T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_source[5:1] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[0] No No No INPUT
tl_rv_dm__regs_i.d_size[1] Yes Yes T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T8 Yes T8 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T8 Yes T8 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T214,*T215,*T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T214,T215,T216 Yes T214,T215,T216 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T5,T6 Yes T4,T18,T45 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T214,T215,T216 Yes T214,T215,T216 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T214,*T215,*T216 Yes T214,T215,T216 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T214,*T215,*T216 Yes T214,T215,T216 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T18,T45 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T214,*T215,*T216 Yes T214,T215,T216 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T214,T215,T216 Yes T214,T215,T216 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T18,T45 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T214,T215,T216 Yes T214,T215,T216 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T60,T61,T20 Yes T60,T61,T20 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T20,T58,T56 Yes T20,T58,T56 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T112,T113,T8 Yes T112,T113,T8 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T217,*T21,*T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T112,T113,T8 Yes T112,T113,T8 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0] Yes Yes *T8,*T217,*T21 Yes T8,T217,T21 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T217,T21,T218 Yes T217,T21,T218 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T217,T21,T218 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T217,T21,T218 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0] Yes Yes T8,*T112,*T113 Yes T112,T113,T8 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T21,T218,T8 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T217,T21,T218 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[1:0] Yes Yes *T8,*T217,*T21 Yes T8,T217,T21 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T21,T218,T8 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T21,*T218,*T8 Yes T217,T21,T218 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T217,T21,T218 Yes T217,T21,T218 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T63,*T64,*T65 Yes T63,T64,T65 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T66,*T8,*T67 Yes T66,T8,T67 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T115,T213,T211 Yes T115,T213,T211 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T63,*T64,*T65 Yes T63,T64,T65 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T42,T43,T44 Yes T42,T43,T44 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T25,T112,T109 Yes T25,T112,T109 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T18,*T25,*T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T18,*T25,*T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T25,T112,T109 Yes T25,T112,T109 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T103,*T18,*T25 Yes T103,T18,T25 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T25,*T26,*T108 Yes T25,T26,T108 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T18,T25,T109 Yes T18,T25,T109 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T18,T25,T112 Yes T18,T25,T112 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T18,T25,T112 Yes T18,T25,T112 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T25,T109,T26 Yes T25,T109,T26 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T18,T25,T109 Yes T18,T25,T112 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T18,T25,T26 Yes T18,T25,T112 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T25,T109,T26 Yes T25,T109,T26 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T103,*T18,*T25 Yes T103,T18,T25 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T18,T25,T26 Yes T18,T25,T112 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T18,*T25,*T109 Yes T18,T25,T109 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T18,T25,T112 Yes T18,T25,T112 INPUT
tl_spi_host1_o.d_ready Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T112,T109,T47 Yes T112,T109,T47 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T18,*T112,*T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T112,T109,T47 Yes T112,T109,T47 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T103,*T18,*T109 Yes T103,T18,T109 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T18,T109,T47 Yes T18,T109,T47 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T18,T112,T109 Yes T18,T112,T109 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T18,T112,T109 Yes T18,T112,T109 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T109,T47,T184 Yes T109,T47,T184 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T18,T109,T47 Yes T18,T112,T109 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T18,T47,T185 Yes T18,T112,T109 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T109,T47,T184 Yes T109,T47,T184 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T103,*T18,*T109 Yes T103,T18,T109 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T18,T47,T185 Yes T18,T112,T109 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T18,*T109,*T47 Yes T18,T109,T47 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T18,T112,T109 Yes T18,T112,T109 INPUT
tl_usbdev_o.d_ready Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T18,*T1,*T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[0] No No No OUTPUT
tl_usbdev_o.a_source[1] Yes Yes *T18,*T2,*T3 Yes T18,T2,T3 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T18,T124,T31 Yes T18,T124,T31 OUTPUT
tl_usbdev_o.a_valid Yes Yes T18,T1,T2 Yes T18,T1,T2 OUTPUT
tl_usbdev_i.a_ready Yes Yes T18,T1,T2 Yes T18,T1,T2 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T18,T31,T145 Yes T18,T124,T31 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T18,*T124,T31 Yes T18,T31,T145 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T18,T1,T3 Yes T18,T1,T2 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T18,T1,T2 Yes T18,T1,T3 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[0] No No No INPUT
tl_usbdev_i.d_source[1] Yes Yes *T18,*T3,*T31 Yes T18,T2,T3 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T18,T1,T3 Yes T18,T1,T2 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T18,*T1,*T2 Yes T18,T1,T3 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T18,T1,T2 Yes T18,T1,T2 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[1:0] Yes Yes *T103,*T4,*T5 Yes T103,T4,T5 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T4,T18,T45 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T6,T18 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[1:0] Yes Yes *T103,*T4,*T5 Yes T103,T4,T5 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0] Yes Yes *T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[0] Yes Yes *T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_size[1] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2] Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T103 Yes T103 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0] Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4] Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[0] Yes Yes *T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_source[5:1] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[0] No No No INPUT
tl_flash_ctrl__prim_i.d_size[1] Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T103 Yes T103 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T103 Yes T103 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T4,T18,T45 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T20,T58,T204 Yes T20,T58,T204 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T20,T58,T204 Yes T20,T58,T204 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T205,*T206,*T20 Yes T205,T206,T20 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T20,T58,T204 Yes T20,T58,T204 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[1:0] Yes Yes *T103,*T206,*T20 Yes T103,T206,T20 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T204,*T135,*T207 Yes T204,T135,T207 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_hmac_o.a_valid Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_hmac_i.a_ready Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes *T205,*T206,T20 Yes T205,T206,T20 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T20,T58,T204 Yes T20,T58,T204 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[1:0] Yes Yes *T103,*T206,*T20 Yes T103,T206,T20 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T20,*T58,*T204 Yes T20,T58,T204 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_kmac_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T4,T45,T165 Yes T4,T45,T165 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T4,*T45,*T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T4,T45,T165 Yes T4,T45,T165 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T103,*T121,*T4 Yes T103,T121,T4 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T130,*T133,*T219 Yes T130,T133,T219 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_o.a_valid Yes Yes T4,T45,T205 Yes T4,T45,T205 OUTPUT
tl_kmac_i.a_ready Yes Yes T4,T45,T205 Yes T4,T45,T205 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T4,T45,T205 Yes T4,T45,T205 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T4,T45,T205 Yes T4,T45,T205 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes *T205,T158,T144 Yes T4,T45,T205 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T4,T45,T152 Yes T165,T158,T173 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T103,*T121,*T4 Yes T103,T121,T4 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T205,T158,T144 Yes T4,T45,T205 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T4,*T45,*T152 Yes T158,T144,T220 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T4,T45,T205 Yes T4,T45,T205 INPUT
tl_aes_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T45,T81,T221 Yes T45,T81,T221 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T45,*T81,*T221 Yes T45,T81,T221 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T45,*T205,*T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T45,T81,T221 Yes T45,T81,T221 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[0] No No No OUTPUT
tl_aes_o.a_source[1] Yes Yes *T45,*T205,*T81 Yes T45,T205,T81 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_o.a_valid Yes Yes T45,T205,T206 Yes T45,T205,T206 OUTPUT
tl_aes_i.a_ready Yes Yes T45,T205,T206 Yes T45,T205,T206 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T45,T205,T206 Yes T45,T205,T206 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T45,T81,T221 Yes T45,T81,T221 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T205,T206,T222 Yes T45,T205,T206 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T45,T205,T206 Yes T45,T205,T206 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[0] No No No INPUT
tl_aes_i.d_source[1] Yes Yes *T45,*T205,*T81 Yes T45,T205,T81 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T205,T206,T222 Yes T45,T205,T206 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T45,*T205,*T206 Yes T45,T205,T206 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T45,T205,T206 Yes T45,T205,T206 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[1:0] Yes Yes *T103,*T4,*T5 Yes T103,T4,T5 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T4,T45,T58 Yes T4,T45,T58 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes T4,*T18,T45 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[1:0] Yes Yes *T103,*T4,*T18 Yes T103,T4,T5 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T4,*T45,*T79 Yes T4,T45,T58 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T4,T45,T223 Yes T4,T45,T223 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T4,T45,T223 Yes T4,T45,T223 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T4,T45,T223 Yes T4,T45,T223 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes T4,*T18,T45 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T4,*T45,*T223 Yes T4,T45,T223 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[1:0] Yes Yes *T103,*T4,*T5 Yes T103,T4,T5 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes T4,*T18,T45 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[1:0] Yes Yes *T103,*T4,*T18 Yes T103,T4,T5 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T4,*T45,*T79 Yes T4,T45,T79 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T4,*T45,*T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T4,*T45,*T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_o.a_valid Yes Yes T4,T45,T79 Yes T4,T45,T79 OUTPUT
tl_edn1_i.a_ready Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes *T82,*T83,*T86 Yes T4,T45,T79 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T82,T83,T86 Yes T4,T45,T79 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T4,*T45,*T79 Yes T4,T45,T79 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T4,T45,T79 Yes T4,T45,T79 INPUT
tl_rv_plic_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T103,*T5,*T6 Yes T103,T5,T6 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T5,T6,T115 Yes T5,T6,T115 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T115,T116,T166 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T103,*T5,*T6 Yes T103,T5,T6 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T115,T116,T166 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T5,*T6,*T115 Yes T5,T6,T115 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_otbn_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T20,T58,T180 Yes T20,T58,T180 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T205,*T206,*T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T20,T58,T180 Yes T20,T58,T180 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T66,*T67,*T224 Yes T66,T67,T224 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_o.a_valid Yes Yes T205,T206,T20 Yes T205,T206,T20 OUTPUT
tl_otbn_i.a_ready Yes Yes T205,T206,T20 Yes T205,T206,T20 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T20,T58,T180 Yes T20,T58,T180 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T206,T20,T58 Yes T206,T20,T58 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes *T206,T20,T58 Yes T206,T20,T58 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T206,T20,T58 Yes T206,T20,T58 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T66,*T67,*T224 Yes T66,T67,T224 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T206,T20,T58 Yes T206,T20,T58 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T20,*T58,*T180 Yes T20,T58,T180 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T206,T20,T58 Yes T206,T20,T58 INPUT
tl_keymgr_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T4,*T45,*T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T4,*T45,*T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_o.a_valid Yes Yes T4,T45,T59 Yes T4,T45,T59 OUTPUT
tl_keymgr_i.a_ready Yes Yes T4,T45,T59 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T59,T158,*T144 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T4,T45,T59 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[1:0] Yes Yes *T103,*T4,*T45 Yes T103,T4,T45 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T59,T158,T144 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T4,*T45,*T59 Yes T4,T45,T59 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T4,T45,T59 Yes T4,T45,T59 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0] Yes Yes *T8,*T4,*T5 Yes T8,T4,T5 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T8 Yes T8 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T5,T6,T115 Yes T5,T6,T115 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0] Yes Yes *T8,*T4,*T5 Yes T8,T4,T5 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T4,T18,T45 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T4,T18,T45 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T78,*T20,*T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T78,T225,T226 Yes T78,T225,T226 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T78,*T20,*T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T227,*T103,*T78 Yes T227,T103,T78 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T78,T225,T226 Yes T78,T225,T226 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T78,T20,T58 Yes T78,T20,T58 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T78,T20,T58 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T132,*T177,*T228 Yes T132,T177,T228 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T78,T20,T56 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes T78,*T20,*T56 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T78,T20,T56 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T103,*T78,*T20 Yes T227,T103,T78 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T78,T20,T56 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T78,*T132,*T177 Yes T78,T225,T226 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T78,T20,T58 Yes T78,T20,T58 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T4,T18,T45 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%