Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T178,T299
0	1	Covered	T176,T178,T299
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T178,T299
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T178,T299

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1018440070	1001110968	0	0
CheckNGreaterZero_A	2026	2026	0	0
GntImpliesReady_A	1018440070	8381	0	0
GntImpliesValid_A	1018440070	8381	0	0
GrantKnown_A	1018440070	1001110968	0	0
IdxKnown_A	1018440070	1001110968	0	0
IndexIsCorrect_A	1018440070	8381	0	0
NoReadyValidNoGrant_A	1018440070	0	0	0
Priority_A	1018440070	8381	0	0
ReadyAndValidImplyGrant_A	1018440070	8381	0	0
ReqAndReadyImplyGrant_A	1018440070	8381	0	0
ReqImpliesValid_A	1018440070	8381	0	0
ValidKnown_A	1018440070	1001110968	0	0
gen_data_port_assertion.DataFlow_A	1018440070	8381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	1001110968	0	0
T4	978292	978044	0	0
T5	276580	276478	0	0
T6	417032	416922	0	0
T18	1177520	1176952	0	0
T45	1628996	1628756	0	0
T59	518904	518678	0	0
T75	315098	314996	0	0
T115	540060	539848	0	0
T116	495024	494798	0	0
T125	757920	757810	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2026	2026	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T45	2	2	0	0
T59	2	2	0	0
T75	2	2	0	0
T115	2	2	0	0
T116	2	2	0	0
T125	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	1001110968	0	0
T4	978292	978044	0	0
T5	276580	276478	0	0
T6	417032	416922	0	0
T18	1177520	1176952	0	0
T45	1628996	1628756	0	0
T59	518904	518678	0	0
T75	315098	314996	0	0
T115	540060	539848	0	0
T116	495024	494798	0	0
T125	757920	757810	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	1001110968	0	0
T4	978292	978044	0	0
T5	276580	276478	0	0
T6	417032	416922	0	0
T18	1177520	1176952	0	0
T45	1628996	1628756	0	0
T59	518904	518678	0	0
T75	315098	314996	0	0
T115	540060	539848	0	0
T116	495024	494798	0	0
T125	757920	757810	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	1001110968	0	0
T4	978292	978044	0	0
T5	276580	276478	0	0
T6	417032	416922	0	0
T18	1177520	1176952	0	0
T45	1628996	1628756	0	0
T59	518904	518678	0	0
T75	315098	314996	0	0
T115	540060	539848	0	0
T116	495024	494798	0	0
T125	757920	757810	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018440070	8381	0	0
T124	122184	0	0	0
T150	961876	0	0	0
T160	488306	0	0	0
T176	219566	2794	0	0
T178	0	2794	0	0
T257	156698	0	0	0
T268	250464	0	0	0
T299	0	2793	0	0
T301	371844	0	0	0
T302	338118	0	0	0
T303	1842022	0	0	0
T304	296568	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T178,T299
0	1	Covered	T176,T178,T299
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T178,T299
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T178,T299

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	509220035	500555484	0	0
CheckNGreaterZero_A	1013	1013	0	0
GntImpliesReady_A	509220035	5191	0	0
GntImpliesValid_A	509220035	5191	0	0
GrantKnown_A	509220035	500555484	0	0
IdxKnown_A	509220035	500555484	0	0
IndexIsCorrect_A	509220035	5191	0	0
NoReadyValidNoGrant_A	509220035	0	0	0
Priority_A	509220035	5191	0	0
ReadyAndValidImplyGrant_A	509220035	5191	0	0
ReqAndReadyImplyGrant_A	509220035	5191	0	0
ReqImpliesValid_A	509220035	5191	0	0
ValidKnown_A	509220035	500555484	0	0
gen_data_port_assertion.DataFlow_A	509220035	5191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	5191	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1731	0	0
T178	0	1730	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1730	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T176,T178,T299
0	1	Covered	T176,T178,T299
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T176,T178,T299
1	Covered	T176,T178,T299

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T176,T178,T299
1	0	Covered	T176,T178,T299
1	1	Covered	T176,T178,T299

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T176,T178,T299

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T176,T178,T299
0	Covered	T176,T178,T299

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	509220035	500555484	0	0
CheckNGreaterZero_A	1013	1013	0	0
GntImpliesReady_A	509220035	3190	0	0
GntImpliesValid_A	509220035	3190	0	0
GrantKnown_A	509220035	500555484	0	0
IdxKnown_A	509220035	500555484	0	0
IndexIsCorrect_A	509220035	3190	0	0
NoReadyValidNoGrant_A	509220035	0	0	0
Priority_A	509220035	3190	0	0
ReadyAndValidImplyGrant_A	509220035	3190	0	0
ReqAndReadyImplyGrant_A	509220035	3190	0	0
ReqImpliesValid_A	509220035	3190	0	0
ValidKnown_A	509220035	500555484	0	0
gen_data_port_assertion.DataFlow_A	509220035	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T45	1	1	0	0
T59	1	1	0	0
T75	1	1	0	0
T115	1	1	0	0
T116	1	1	0	0
T125	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	500555484	0	0
T4	489146	489022	0	0
T5	138290	138239	0	0
T6	208516	208461	0	0
T18	588760	588476	0	0
T45	814498	814378	0	0
T59	259452	259339	0	0
T75	157549	157498	0	0
T115	270030	269924	0	0
T116	247512	247399	0	0
T125	378960	378905	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509220035	3190	0	0
T124	61092	0	0	0
T150	480938	0	0	0
T160	244153	0	0	0
T176	109783	1063	0	0
T178	0	1064	0	0
T257	78349	0	0	0
T268	125232	0	0	0
T299	0	1063	0	0
T301	185922	0	0	0
T302	169059	0	0	0
T303	921011	0	0	0
T304	148284	0	0	0