Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.83 99.34 100.00 100.00 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1013 1013 0 0
OutputsKnown_A 127709062 127021402 0 0
gen_no_flops.OutputDelay_A 127709062 127021402 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1013 1013 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0
T59 1 1 0 0
T75 1 1 0 0
T115 1 1 0 0
T116 1 1 0 0
T125 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 127709062 127021402 0 0
T4 131015 130531 0 0
T5 38298 37564 0 0
T6 56107 55494 0 0
T18 143950 143193 0 0
T45 196886 196238 0 0
T59 63464 63009 0 0
T75 42477 41949 0 0
T115 66057 65549 0 0
T116 60465 60142 0 0
T125 91750 91324 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 127709062 127021402 0 0
T4 131015 130531 0 0
T5 38298 37564 0 0
T6 56107 55494 0 0
T18 143950 143193 0 0
T45 196886 196238 0 0
T59 63464 63009 0 0
T75 42477 41949 0 0
T115 66057 65549 0 0
T116 60465 60142 0 0
T125 91750 91324 0 0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1013 1013 0 0
OutputsKnown_A 127709062 127021402 0 0
gen_no_flops.OutputDelay_A 127709062 127021402 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1013 1013 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0
T59 1 1 0 0
T75 1 1 0 0
T115 1 1 0 0
T116 1 1 0 0
T125 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 127709062 127021402 0 0
T4 131015 130531 0 0
T5 38298 37564 0 0
T6 56107 55494 0 0
T18 143950 143193 0 0
T45 196886 196238 0 0
T59 63464 63009 0 0
T75 42477 41949 0 0
T115 66057 65549 0 0
T116 60465 60142 0 0
T125 91750 91324 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 127709062 127021402 0 0
T4 131015 130531 0 0
T5 38298 37564 0 0
T6 56107 55494 0 0
T18 143950 143193 0 0
T45 196886 196238 0 0
T59 63464 63009 0 0
T75 42477 41949 0 0
T115 66057 65549 0 0
T116 60465 60142 0 0
T125 91750 91324 0 0

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