9edf84e236| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.729m | 2.800ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.077m | 2.568ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.834m | 2.646ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.681m | 2.834ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 11.227m | 3.738ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 11.227m | 3.738ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 11.227m | 3.738ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 14.136m | 4.529ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 14.136m | 4.529ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 13.064m | 5.008ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.788m | 4.454ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.640m | 4.424ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 53.115m | 12.685ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 52.386m | 13.235ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 34.082m | 13.137ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 65 | 220 | 29.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.524m | 5.178ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.524m | 5.178ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.750m | 3.165ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.058m | 7.023ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.884m | 3.311ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 30.382m | 15.109ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 27.596m | 15.186ms | 2 | 5 | 40.00 | ||
| chip_tap_straps_rma | 25.557m | 14.481ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 2.961m | 3.458ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.175m | 3.530ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 27.672m | 10.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 15.333m | 6.385ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 15.333m | 6.385ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 20.839m | 7.338ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 43.928m | 20.419ms | 1 | 3 | 33.33 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.087m | 4.164ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.836m | 5.718ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.110h | 18.326ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.532m | 3.057ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 23.890m | 7.276ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.478m | 3.403ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 26.593m | 9.531ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.156m | 2.434ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.198m | 4.181ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.697m | 3.249ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.346m | 3.482ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 17.545m | 9.196ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.836m | 5.763ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.343m | 2.541ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.836m | 5.763ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.982m | 3.388ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.171m | 3.289ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.937m | 2.818ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.517m | 2.994ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.949m | 2.882ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.638m | 3.621ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 6.049m | 3.619ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.393m | 3.350ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.699m | 3.314ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 21.359m | 7.405ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.399m | 5.680ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 10.484m | 5.578ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.116m | 2.285ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.522m | 3.279ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.461m | 2.988ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.652m | 3.014ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.667m | 3.703ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.822m | 3.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 12.403m | 5.885ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.043h | 78.397ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.191h | 14.812ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.683m | 4.765ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.751m | 4.869ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 12.660m | 10.828ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.060h | 60.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.757h | 65.773ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.191h | 14.812ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.011h | 25.731ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.211h | 15.224ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 49.996m | 11.535ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.227h | 15.811ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.184h | 15.266ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.306h | 15.599ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 58.941m | 15.151ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 1.189h | 11.344ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.101h | 15.387ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.212h | 15.166ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.106h | 15.692ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.049h | 14.476ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.507h | 18.936ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.877h | 24.387ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.839h | 24.660ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.682h | 24.406ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.614h | 23.399ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.509h | 17.407ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.709h | 24.323ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.696h | 23.319ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.503h | 23.596ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.649h | 22.875ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 52.338m | 11.772ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.201h | 14.843ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.058h | 15.131ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.128h | 15.155ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.037h | 14.382ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 56.816m | 11.213ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.223h | 15.042ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 57.845m | 13.917ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.034h | 15.020ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.067h | 14.461ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 57.111m | 11.747ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.247h | 15.397ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.170h | 15.663ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.238h | 15.799ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.107h | 15.450ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.238h | 14.871ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.107h | 14.542ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 59.693m | 14.147ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.282h | 17.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.123m | 3.364ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.532m | 3.057ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 6.004m | 2.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.575m | 3.335ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 47.267m | 10.548ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.815m | 19.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.815m | 19.239ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.810m | 4.119ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.399m | 5.680ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.810m | 4.119ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.104m | 10.237ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.104m | 10.237ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.183m | 7.194ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.405m | 5.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 19.532m | 6.482ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.575m | 3.335ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.851m | 3.260ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 6.018m | 3.711ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.367m | 4.621ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 11.762m | 4.754ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.738m | 4.336ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.548m | 4.836ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 29.741m | 10.224ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 14.137m | 3.848ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.119m | 4.559ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.032m | 4.065ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.142m | 4.942ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.399m | 3.652ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 13.702m | 4.184ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 20.839m | 7.338ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 19.557m | 11.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.032m | 4.065ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.142m | 4.942ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.087m | 4.164ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.836m | 5.718ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.110h | 18.326ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.532m | 3.057ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 23.890m | 7.276ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.478m | 3.403ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 26.593m | 9.531ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.156m | 2.434ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.198m | 4.181ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.697m | 3.249ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.043m | 2.598ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 11.854m | 5.228ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 23.267m | 6.690ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.203h | 24.849ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 3.976m | 3.300ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.419m | 3.379ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 34.780m | 12.349ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.978m | 2.905ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.929m | 5.422ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 44.920m | 24.005ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 3.342h | 83.447ms | 2 | 3 | 66.67 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 20.839m | 7.338ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 12.707m | 4.259ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 6.687m | 4.129ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 23.250m | 6.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 25.095m | 6.623ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.951m | 5.332ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.917m | 6.780ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.769m | 2.975ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 25.358m | 8.838ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.039m | 22.830ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.467m | 3.694ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.964m | 3.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.508m | 4.767ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.039m | 22.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.039m | 22.830ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.057h | 20.312ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.057h | 20.312ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.490m | 5.051ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.815m | 19.239ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.097h | 30.979ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 3.983m | 3.140ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 22.563m | 7.001ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 3.983m | 3.140ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 25.095m | 6.623ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.428m | 3.106ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 44.369m | 18.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 20.937m | 5.755ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.836m | 5.718ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 13.488m | 4.473ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.087m | 4.164ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.526h | 43.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 44.369m | 18.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.124m | 3.605ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.526h | 43.813ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 21.364m | 5.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 15.328m | 6.020ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 15.328m | 6.020ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.270m | 2.967ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 6.478m | 3.403ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.851m | 3.260ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.683m | 3.145ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 32.705m | 8.092ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.992m | 5.261ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.615m | 5.673ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 17.595m | 5.327ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.520m | 4.772ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 |
| chip_sw_keymgr_key_derivation_jitter_en | 26.593m | 9.531ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 24.992m | 6.718ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 47.267m | 10.548ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.257h | 16.190ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.358m | 3.397ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.665m | 3.032ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.156m | 2.434ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.527m | 3.293ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 6.478m | 3.146ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 6.018m | 3.711ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.671m | 4.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 30.382m | 15.109ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 25.557m | 14.481ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 2.961m | 3.458ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.365m | 2.413ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 33.204m | 10.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 11.498m | 5.359ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.526h | 43.813ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.555m | 4.058ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 20.492m | 7.751ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.446m | 8.116ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.875m | 8.847ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 | ||
| chip_sw_rom_ctrl_integrity_check | 11.312m | 9.499ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.886m | 7.309ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 19.557m | 11.370ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 14.137m | 3.848ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.119m | 4.559ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.032m | 4.065ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.142m | 4.942ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.399m | 3.652ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 13.702m | 4.184ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 30.382m | 15.109ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 25.557m | 14.481ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 2.961m | 3.458ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.640m | 3.322ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.170m | 3.753ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 1.987m | 2.862ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.107m | 4.292ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 43.993m | 28.820ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.686h | 49.305ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.650h | 49.707ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 22.921m | 9.404ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.601h | 45.051ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 43.993m | 28.820ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.114m | 2.405ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.032m | 2.072ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.073m | 2.458ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 44.369m | 18.086ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.659m | 4.239ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 | ||
| chip_sw_sram_ctrl_scrambled_access | 13.457m | 4.030ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.981m | 2.365ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 44.369m | 18.086ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.659m | 4.239ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 31.614m | 8.975ms | 2 | 3 | 66.67 | ||
| chip_sw_sram_ctrl_scrambled_access | 13.457m | 4.030ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.981m | 2.365ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 11.316m | 5.104ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.365m | 2.413ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.555m | 4.058ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 20.492m | 7.751ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.446m | 8.116ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.875m | 8.847ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.824m | 9.494ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.568h | 27.959ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.785m | 8.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 31.465m | 25.366ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.088m | 7.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 14.560m | 8.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 16.308m | 8.142ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 29.091m | 20.600ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 28.850m | 13.984ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 18.104m | 10.237ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 25.800m | 13.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.580m | 5.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.785m | 8.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.355m | 4.750ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 54.974m | 27.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.567m | 5.108ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.607m | 6.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 37.573m | 26.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 25.358m | 8.838ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 28.849m | 12.299ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 42.748m | 28.702ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.348m | 2.988ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.312m | 9.499ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.312m | 9.499ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 28.849m | 12.299ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 37.573m | 26.354ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 11.580m | 5.476ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.399m | 5.680ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 9.567m | 3.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 16.156m | 5.505ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.666m | 4.817ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 35.114m | 14.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.562m | 2.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 36.759m | 8.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.659m | 6.064ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.215m | 4.482ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 14.008m | 4.723ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.099m | 3.192ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.165m | 2.961ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.191h | 14.812ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.457m | 7.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 12.824m | 4.680ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.258m | 4.165ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.817m | 3.038ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 13.457m | 4.030ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.198m | 4.181ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 13.210m | 9.257ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 12.417m | 7.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.886m | 7.309ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 15.333m | 6.385ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.050m | 2.564ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.175m | 3.090ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 9.658m | 3.586ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 7.277m | 3.463ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 35.048m | 8.016ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.184h | 31.384ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 57.221m | 12.240ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.853m | 2.526ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.671m | 4.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.384m | 2.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 35.114m | 14.764ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.394m | 4.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.231m | 4.195ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 33.526m | 13.186ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 23.250m | 6.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 36.759m | 8.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 26.630m | 8.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.831h | 255.774ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 41.879m | 20.649ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 28.841m | 13.659ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 9.567m | 3.577ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.590m | 5.488ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 11.782m | 6.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 25.557m | 14.481ms | 4 | 5 | 80.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 878 | 2644 | 33.21 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.731m | 3.284ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 4.237h | 71.734ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 20.569m | 7.560ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 21.110m | 8.879ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 20.374m | 7.480ms | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 35.991m | 24.478ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 53.787m | 32.050ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 48.558m | 37.362ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 6.352h | 200.019ms | 0 | 3 | 0.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 10.966m | 4.174ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 10.371m | 3.371ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 20.527m | 4.573ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 41.519m | 11.119ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 12.877m | 3.396ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 22.160m | 5.178ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.560m | 2.649ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.687m | 5.198ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 10.280m | 6.285ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 10.083m | 4.853ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 28.849m | 12.299ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.265m | 6.072ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 14.136m | 4.529ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.428h | 18.632ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 20.569m | 7.560ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 21.110m | 8.879ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 20.374m | 7.480ms | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.204m | 6.328ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 36 | 48 | 75.00 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.993m | 3.122ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.103m | 5.260ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.515m | 3.491ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.035h | 16.838ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 19.700m | 6.155ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 15.944m | 5.362ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 9.702m | 4.561ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.857m | 5.843ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.699m | 2.892ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.294m | 2.925ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 6.971m | 3.516ms | 3 | 3 | 100.00 | ||
| TOTAL | 1013 | 2948 | 34.36 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 10 | 90.91 |
| V1 | 18 | 18 | 12 | 66.67 |
| V2 | 285 | 270 | 242 | 84.91 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 22 | 16 | 17.78 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.78 | 93.44 | 83.31 | 90.83 | -- | 94.70 | 97.53 | 84.87 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.105253411232491880394879358010826138340985372371054670262322629010967249068867
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.13026478717022230493130112138170390250932728434993029731650605724141863754994
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.113236741905838259786886708805871537586359175041507574375074623401293433952044
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.79329553253433830409994189061647292359202321892519258058596429568527566006702
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.51366033477857442018215731149363032028856284660234266820326875728859893346327
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.26924786241169661634164703309416689667292907189592605644461711241527567155087
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.16064792625947341694635050842804065526587229358277734301058487908017390442535
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.21211371598886432152799416226235371303734583120106402904345248952842764188053
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.29754405992949221101341443606527729030668909148711593265849935066170718964781
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.33687209271112189675790698524181493455326893481583844318136899496737970808461
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.70786048781762828952502342841327646959365899133480470639730586607115247633448
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.42266064706758347203063134462736511261619326682861332650178261491582098342623
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.35886693357425738981985336916703003304298728450727511625170761227333968253646
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.25063655697513290504548720522393974149160717669865467914776692275559308429079
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.50527314675070807760359049648941073916388890493666684207417865780663868686161
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.23402047447999225632846900347016156369234115730469770379969480790537809301319
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.35153501948434058588447494579490114787145997495621863538027129165914553826362
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.36543587834843190540944893283944935753733183441357113523239280791781363243470
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.112632390775569449298390598870898084753826845015598401908822197899678541264430
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.64919788475587741783673908983239086442503072027363037021644272105256413906907
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.106701744373700782761752555333354630409485329478324286094140253281866294831918
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:391191f7-94bf-4c18-87a2-3dc6facc1f1a
1.chip_sw_rv_timer_systick_test.44607817565655596035227696344684536491626532708799048647775603046764030759542
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:10ef4a46-29b5-4aa3-9b31-f8e1ac539100
... and 1 more failures.
Test chip_sw_ast_clk_rst_inputs has 2 failures.
0.chip_sw_ast_clk_rst_inputs.28375289675352002032994367848063186050864781995470262501916799066175312207803
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:7c280f5e-47e4-4363-83c0-e3f807564971
2.chip_sw_ast_clk_rst_inputs.48871830710712409271716619228596561142510062020976108440407301469553069540660
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:6bea17a9-a015-4095-aafe-5ac65a2b911d
Test chip_sw_power_virus has 3 failures.
0.chip_sw_power_virus.24754475358671805848721926102513407375666902040840145727820114762240807457626
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:6188097c-b67c-4a37-b456-353c43094b4f
1.chip_sw_power_virus.55497282237023670281424277285952516062847610334567017466369169281114990703191
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:10acbd2b-e623-4a21-ae83-b272742da528
... and 1 more failures.
Test chip_sw_keymgr_key_derivation has 1 failures.
1.chip_sw_keymgr_key_derivation.115751218697758356369568168013613474208603863712265474457080580240642726118336
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
Job ID: smart:22e52be9-4771-484a-a6aa-8bf782e1d476
Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
2.chip_sw_csrng_edn_concurrency_reduced_freq.87225818873129187857643026394324973808821587035309611045517618254622368915562
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job ID: smart:790fed9f-78f6-48c4-a004-20ccd279b54f
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 4 failures:
0.chip_tap_straps_testunlock0.21656839161685755774703556416662339507882909094612681189197629703081677461588
Line 5994, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest/run.log
UVM_FATAL @ 15185.698661 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 15185.698661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_tap_straps_testunlock0.41644751730961295649694871916099721788703710157993708232680835024795280570349
Line 5963, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest/run.log
UVM_FATAL @ 14306.664424 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 14306.664424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
1.chip_tap_straps_rma.94437923688842193610996409082767214097250622877845711052723669067768066213491
Line 5943, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 14481.123947 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
UVM_INFO @ 14481.123947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_debug_test_unlocked0.97165713021290121123354089204510778968901786688874603553807531129216390841452
Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
UVM_FATAL @ 7560.277000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 7560.277000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_dev has 1 failures.
0.rom_e2e_jtag_debug_dev.108969519562338710635052675087277113627154387230539729247053631316332378896736
Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
UVM_FATAL @ 8879.399000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 8879.399000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_rma has 1 failures.
0.rom_e2e_jtag_debug_rma.33153313472289643710705345254380159239724872687198517933467595146209257310532
Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
UVM_FATAL @ 7480.062500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 7480.062500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.88733416791632938090850221644837813752010894462544764634851457948655526495413
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2367.038964 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2367.038964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_rv_core_ibex_lockstep_glitch.20499468669481723987497365864697897052866805234908900325701988848954309964172
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2924.917316 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2924.917316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:
1.rom_e2e_self_hash.106448307413770969140776847721480199835831493500806775158951024857554462179322
Line 1008, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
UVM_ERROR @ 200018.788044 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 200018.788044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_e2e_self_hash.33924497900942934119772905515230140783789089178876984606919245495672043310403
Line 1011, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log
UVM_ERROR @ 200015.092812 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 200015.092812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
0.rom_e2e_self_hash.79683893259354434441338610224647861909866633687809494274159792004017496987612
Line 1013, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 72598.349243 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 72598.349243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
38.chip_sw_all_escalation_resets.19256888343946794475895713907482403147862381771128223008477918712223490552091
Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2883.852000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2883.852000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
62.chip_sw_alert_handler_lpg_sleep_mode_alerts.63055526672611927336100126225034948570215144212580671132601099023450100952287
Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3819.531424 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 3819.531424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---