CHIP Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 chip_sw_example_tests chip_sw_example_flash 5.172m 2.423ms 3 3 100.00
chip_sw_example_rom 2.126m 2.391ms 3 3 100.00
chip_sw_example_manufacturer 4.250m 2.642ms 3 3 100.00
chip_sw_example_concurrency 6.259m 2.946ms 3 3 100.00
V1 csr_hw_reset chip_csr_hw_reset 0 5 0.00
V1 csr_rw chip_csr_rw 0 20 0.00
V1 csr_bit_bash chip_csr_bit_bash 0 5 0.00
V1 csr_aliasing chip_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset chip_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr chip_csr_aliasing 0 5 0.00
chip_csr_rw 0 20 0.00
V1 xbar_smoke xbar_smoke 0 100 0.00
V1 chip_sw_gpio_out chip_sw_gpio 11.028m 3.516ms 3 3 100.00
V1 chip_sw_gpio_in chip_sw_gpio 11.028m 3.516ms 3 3 100.00
V1 chip_sw_gpio_irq chip_sw_gpio 11.028m 3.516ms 3 3 100.00
V1 chip_sw_uart_tx_rx chip_sw_uart_tx_rx 11.861m 4.174ms 5 5 100.00
V1 chip_sw_uart_rx_overflow chip_sw_uart_tx_rx 11.861m 4.174ms 5 5 100.00
chip_sw_uart_tx_rx_idx1 13.425m 4.308ms 5 5 100.00
chip_sw_uart_tx_rx_idx2 12.286m 4.184ms 5 5 100.00
chip_sw_uart_tx_rx_idx3 13.939m 4.221ms 5 5 100.00
V1 chip_sw_uart_baud_rate chip_sw_uart_rand_baudrate 36.803m 12.490ms 20 20 100.00
V1 chip_sw_uart_tx_rx_alt_clk_freq chip_sw_uart_tx_rx_alt_clk_freq 30.184m 8.600ms 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 35.394m 13.053ms 5 5 100.00
V1 TOTAL 65 220 29.55
V2 chip_pin_mux chip_padctrl_attributes 4.843m 5.693ms 10 10 100.00
V2 chip_padctrl_attributes chip_padctrl_attributes 4.843m 5.693ms 10 10 100.00
V2 chip_sw_sleep_pin_mio_dio_val chip_sw_sleep_pin_mio_dio_val 5.336m 3.221ms 3 3 100.00
V2 chip_sw_sleep_pin_wake chip_sw_sleep_pin_wake 5.639m 3.232ms 3 3 100.00
V2 chip_sw_sleep_pin_retention chip_sw_sleep_pin_retention 5.994m 4.529ms 3 3 100.00
V2 chip_sw_tap_strap_sampling chip_tap_straps_dev 25.658m 16.187ms 5 5 100.00
chip_tap_straps_testunlock0 21.327m 13.082ms 3 5 60.00
chip_tap_straps_rma 29.880m 14.990ms 4 5 80.00
chip_tap_straps_prod 30.627m 16.908ms 5 5 100.00
V2 chip_sw_pattgen_ios chip_sw_pattgen_ios 4.869m 2.258ms 3 3 100.00
V2 chip_sw_sleep_pwm_pulses chip_sw_sleep_pwm_pulses 24.051m 9.253ms 3 3 100.00
V2 chip_sw_data_integrity chip_sw_data_integrity_escalation 14.589m 4.544ms 6 6 100.00
V2 chip_sw_instruction_integrity chip_sw_data_integrity_escalation 14.589m 4.544ms 6 6 100.00
V2 chip_sw_ast_clk_outputs chip_sw_ast_clk_outputs 16.805m 7.878ms 3 3 100.00
V2 chip_sw_ast_clk_rst_inputs chip_sw_ast_clk_rst_inputs 0 3 0.00
V2 chip_sw_ast_sys_clk_jitter chip_sw_flash_ctrl_ops_jitter_en 14.822m 4.097ms 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 20.547m 5.729ms 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 1.131h 18.201ms 3 3 100.00
chip_sw_aes_enc_jitter_en 6.142m 3.404ms 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 21.953m 6.961ms 3 3 100.00
chip_sw_hmac_enc_jitter_en 5.810m 3.659ms 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 42.239m 12.623ms 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 6.175m 3.399ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 13.051m 5.773ms 3 3 100.00
chip_sw_clkmgr_jitter 5.079m 2.506ms 3 3 100.00
V2 chip_sw_ast_usb_clk_calib chip_sw_usb_ast_clk_calib 8.147m 2.980ms 1 1 100.00
V2 chip_sw_sensor_ctrl_ast_alerts chip_sw_sensor_ctrl_alert 16.761m 9.252ms 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 8.764m 5.463ms 3 3 100.00
V2 chip_sw_sensor_ctrl_ast_status chip_sw_sensor_ctrl_status 5.346m 2.276ms 3 3 100.00
V2 chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 8.764m 5.463ms 3 3 100.00
V2 chip_sw_smoketest chip_sw_flash_scrambling_smoketest 5.153m 2.845ms 3 3 100.00
chip_sw_aes_smoketest 5.204m 3.186ms 3 3 100.00
chip_sw_aon_timer_smoketest 6.214m 2.635ms 3 3 100.00
chip_sw_clkmgr_smoketest 5.934m 3.555ms 3 3 100.00
chip_sw_csrng_smoketest 4.497m 2.847ms 3 3 100.00
chip_sw_entropy_src_smoketest 8.391m 3.263ms 3 3 100.00
chip_sw_gpio_smoketest 5.566m 3.219ms 3 3 100.00
chip_sw_hmac_smoketest 6.277m 3.272ms 3 3 100.00
chip_sw_kmac_smoketest 6.062m 2.797ms 3 3 100.00
chip_sw_otbn_smoketest 42.080m 11.177ms 3 3 100.00
chip_sw_pwrmgr_smoketest 8.826m 6.803ms 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 10.377m 6.680ms 3 3 100.00
chip_sw_rv_plic_smoketest 4.497m 3.280ms 3 3 100.00
chip_sw_rv_timer_smoketest 4.463m 2.982ms 3 3 100.00
chip_sw_rstmgr_smoketest 4.254m 2.256ms 3 3 100.00
chip_sw_sram_ctrl_smoketest 5.152m 2.503ms 3 3 100.00
chip_sw_uart_smoketest 4.326m 3.405ms 3 3 100.00
V2 chip_sw_otp_smoketest chip_sw_otp_ctrl_smoketest 4.567m 2.896ms 3 3 100.00
V2 chip_sw_rom_functests rom_keymgr_functest 10.793m 3.920ms 3 3 100.00
V2 chip_sw_boot chip_sw_uart_tx_rx_bootstrap 4.792h 78.787ms 3 3 100.00
V2 chip_sw_secure_boot rom_e2e_smoke 1.238h 14.768ms 3 3 100.00
V2 chip_sw_rom_raw_unlock rom_raw_unlock 5.272h 300.052ms 0 3 0.00
V2 chip_sw_power_idle_load chip_sw_power_idle_load 15.011m 4.936ms 3 3 100.00
V2 chip_sw_power_sleep_load chip_sw_power_sleep_load 8.456m 5.122ms 3 3 100.00
V2 chip_sw_exit_test_unlocked_bootstrap chip_sw_exit_test_unlocked_bootstrap 3.236h 58.970ms 2 3 66.67
V2 chip_sw_inject_scramble_seed chip_sw_inject_scramble_seed 3.854h 65.926ms 3 3 100.00
V2 tl_d_oob_addr_access chip_tl_errors 0 30 0.00
V2 tl_d_illegal_access chip_tl_errors 0 30 0.00
V2 tl_d_outstanding_access chip_csr_aliasing 0 5 0.00
chip_same_csr_outstanding 0 20 0.00
chip_csr_hw_reset 0 5 0.00
chip_csr_rw 0 20 0.00
V2 tl_d_partial_access chip_csr_aliasing 0 5 0.00
chip_same_csr_outstanding 0 20 0.00
chip_csr_hw_reset 0 5 0.00
chip_csr_rw 0 20 0.00
V2 xbar_base_random_sequence xbar_random 0 100 0.00
V2 xbar_random_delay xbar_smoke_zero_delays 0 100 0.00
xbar_smoke_large_delays 0 100 0.00
xbar_smoke_slow_rsp 0 100 0.00
xbar_random_zero_delays 0 100 0.00
xbar_random_large_delays 0 100 0.00
xbar_random_slow_rsp 0 100 0.00
V2 xbar_unmapped_address xbar_unmapped_addr 0 100 0.00
xbar_error_and_unmapped_addr 0 100 0.00
V2 xbar_error_cases xbar_error_random 0 100 0.00
xbar_error_and_unmapped_addr 0 100 0.00
V2 xbar_all_access_same_device xbar_access_same_device 0 100 0.00
xbar_access_same_device_slow_rsp 0 100 0.00
V2 xbar_all_hosts_use_same_source_id xbar_same_source 0 100 0.00
V2 xbar_stress_all xbar_stress_all 0 100 0.00
xbar_stress_all_with_error 0 100 0.00
V2 xbar_stress_with_reset xbar_stress_all_with_rand_reset 0 100 0.00
xbar_stress_all_with_reset_error 0 100 0.00
V2 rom_e2e_smoke rom_e2e_smoke 1.238h 14.768ms 3 3 100.00
V2 rom_e2e_shutdown_output rom_e2e_shutdown_output 1.165h 29.617ms 3 3 100.00
V2 rom_e2e_shutdown_exception_c rom_e2e_shutdown_exception_c 1.187h 15.200ms 3 3 100.00
V2 rom_e2e_boot_policy_valid rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 50.562m 11.171ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 1.031h 15.718ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 1.141h 14.896ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 1.329h 15.192ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 1.113h 15.195ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 52.181m 11.975ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 1.213h 15.373ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 1.286h 15.390ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 1.355h 15.753ms 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 1.153h 14.836ms 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 1.581h 18.091ms 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 1.990h 24.861ms 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 2.003h 24.764ms 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 2.078h 24.495ms 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 1.627h 23.571ms 1 1 100.00
V2 rom_e2e_sigverify_always rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 1.460h 17.525ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 1.791h 23.455ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 1.618h 23.230ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 1.639h 22.681ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 1.859h 21.903ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 48.323m 10.078ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 1.090h 13.745ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 1.114h 13.593ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 1.163h 13.703ms 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 1.178h 12.811ms 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 57.702m 10.440ms 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 1.107h 14.472ms 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 1.085h 14.931ms 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 1.110h 15.017ms 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 58.147m 13.916ms 0 1 0.00
V2 rom_e2e_asm_init rom_e2e_asm_init_test_unlocked0 56.459m 11.736ms 3 3 100.00
rom_e2e_asm_init_dev 1.372h 15.321ms 3 3 100.00
rom_e2e_asm_init_prod 1.094h 15.158ms 3 3 100.00
rom_e2e_asm_init_prod_end 1.214h 15.808ms 3 3 100.00
rom_e2e_asm_init_rma 1.141h 14.882ms 3 3 100.00
V2 rom_e2e_keymgr_init rom_e2e_keymgr_init_rom_ext_meas 1.205h 14.428ms 3 3 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 1.099h 15.118ms 3 3 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 1.285h 14.911ms 3 3 100.00
V2 rom_e2e_static_critical rom_e2e_static_critical 1.241h 17.046ms 3 3 100.00
V2 chip_sw_aes_enc chip_sw_aes_enc 5.170m 2.467ms 3 3 100.00
chip_sw_aes_enc_jitter_en 6.142m 3.404ms 3 3 100.00
V2 chip_sw_aes_multi_block chip_sw_aes_multi_block 0 0 --
V2 chip_sw_aes_interrupt_encryption chip_sw_aes_interrupt_encryption 0 0 --
V2 chip_sw_aes_entropy chip_sw_aes_entropy 6.317m 2.291ms 3 3 100.00
V2 chip_sw_aes_prng_reseed chip_sw_aes_prng_reseed 0 0 --
V2 chip_sw_aes_force_prng_reseed chip_sw_aes_force_prng_reseed 0 0 --
V2 chip_sw_aes_idle chip_sw_aes_idle 5.303m 2.810ms 3 3 100.00
V2 chip_sw_aes_sideload chip_sw_keymgr_sideload_aes 37.885m 10.821ms 3 3 100.00
V2 chip_sw_adc_ctrl_debug_cable_irq chip_sw_adc_ctrl_sleep_debug_cable_wakeup 11.199m 19.334ms 3 3 100.00
V2 chip_sw_adc_ctrl_sleep_debug_cable_wakeup chip_sw_adc_ctrl_sleep_debug_cable_wakeup 11.199m 19.334ms 3 3 100.00
V2 chip_sw_aon_timer_wakeup_irq chip_sw_aon_timer_irq 9.549m 3.503ms 3 3 100.00
V2 chip_sw_aon_timer_sleep_wakeup chip_sw_pwrmgr_smoketest 8.826m 6.803ms 3 3 100.00
V2 chip_sw_aon_timer_wdog_bark_irq chip_sw_aon_timer_irq 9.549m 3.503ms 3 3 100.00
V2 chip_sw_aon_timer_wdog_bite_reset chip_sw_aon_timer_wdog_bite_reset 13.284m 8.725ms 3 3 100.00
V2 chip_sw_aon_timer_sleep_wdog_bite_reset chip_sw_aon_timer_wdog_bite_reset 13.284m 8.725ms 3 3 100.00
V2 chip_sw_aon_timer_sleep_wdog_sleep_pause chip_sw_aon_timer_sleep_wdog_sleep_pause 9.565m 7.630ms 5 5 100.00
V2 chip_sw_aon_timer_wdog_lc_escalate chip_sw_aon_timer_wdog_lc_escalate 14.934m 5.487ms 3 3 100.00
V2 chip_sw_clkmgr_idle_trans chip_sw_otbn_randomness 20.033m 6.412ms 3 3 100.00
chip_sw_aes_idle 5.303m 2.810ms 3 3 100.00
chip_sw_hmac_enc_idle 5.566m 3.341ms 3 3 100.00
chip_sw_kmac_idle 5.266m 3.525ms 3 3 100.00
V2 chip_sw_clkmgr_off_trans chip_sw_clkmgr_off_aes_trans 10.091m 4.829ms 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 10.115m 4.604ms 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 8.224m 4.165ms 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 9.590m 4.516ms 3 3 100.00
V2 chip_sw_clkmgr_off_peri chip_sw_clkmgr_off_peri 24.933m 10.287ms 3 3 100.00
V2 chip_sw_clkmgr_div chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 15.075m 4.017ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 13.146m 4.153ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 9.994m 3.878ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 11.937m 5.139ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 12.405m 3.921ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 13.346m 4.330ms 3 3 100.00
chip_sw_ast_clk_outputs 16.805m 7.878ms 3 3 100.00
V2 chip_sw_clkmgr_external_clk_src_for_lc chip_sw_clkmgr_external_clk_src_for_lc 19.270m 12.461ms 3 3 100.00
V2 chip_sw_clkmgr_external_clk_src_for_sw chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 9.994m 3.878ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 11.937m 5.139ms 3 3 100.00
V2 chip_sw_clkmgr_jitter chip_sw_flash_ctrl_ops_jitter_en 14.822m 4.097ms 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 20.547m 5.729ms 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 1.131h 18.201ms 3 3 100.00
chip_sw_aes_enc_jitter_en 6.142m 3.404ms 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 21.953m 6.961ms 3 3 100.00
chip_sw_hmac_enc_jitter_en 5.810m 3.659ms 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 42.239m 12.623ms 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 6.175m 3.399ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 13.051m 5.773ms 3 3 100.00
chip_sw_clkmgr_jitter 5.079m 2.506ms 3 3 100.00
V2 chip_sw_clkmgr_extended_range chip_sw_clkmgr_jitter_reduced_freq 4.204m 2.704ms 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 12.049m 4.578ms 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 22.573m 7.200ms 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 1.281h 24.063ms 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 4.400m 2.926ms 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 5.212m 3.589ms 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 32.145m 10.574ms 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 5.213m 3.262ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 10.800m 4.542ms 3 3 100.00
chip_sw_flash_init_reduced_freq 42.861m 21.863ms 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 1.348h 22.055ms 3 3 100.00
V2 chip_sw_clkmgr_deep_sleep_frequency chip_sw_ast_clk_outputs 16.805m 7.878ms 3 3 100.00
V2 chip_sw_clkmgr_sleep_frequency chip_sw_clkmgr_sleep_frequency 11.673m 4.529ms 3 3 100.00
V2 chip_sw_clkmgr_reset_frequency chip_sw_clkmgr_reset_frequency 8.315m 3.945ms 3 3 100.00
V2 chip_sw_clkmgr_escalation_reset chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V2 chip_sw_clkmgr_alert_handler_clock_enables chip_sw_alert_handler_lpg_clkoff 36.101m 8.380ms 3 3 100.00
V2 chip_sw_csrng_edn_cmd chip_sw_entropy_src_csrng 32.989m 7.970ms 3 3 100.00
V2 chip_sw_csrng_fuse_en_sw_app_read chip_sw_csrng_fuse_en_sw_app_read_test 8.419m 4.064ms 3 3 100.00
V2 chip_sw_csrng_lc_hw_debug_en chip_sw_csrng_lc_hw_debug_en_test 15.188m 5.663ms 3 3 100.00
V2 chip_sw_csrng_known_answer_tests chip_sw_csrng_kat_test 4.950m 3.041ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_reset chip_sw_pwrmgr_sysrst_ctrl_reset 18.216m 7.951ms 3 3 100.00
chip_sw_sysrst_ctrl_reset 35.122m 22.876ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_inputs chip_sw_sysrst_ctrl_inputs 6.371m 3.733ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_outputs chip_sw_sysrst_ctrl_outputs 7.164m 3.415ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_in_irq chip_sw_sysrst_ctrl_in_irq 12.078m 4.479ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_sleep_wakeup chip_sw_sysrst_ctrl_reset 35.122m 22.876ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_sleep_reset chip_sw_sysrst_ctrl_reset 35.122m 22.876ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_ec_rst_l chip_sw_sysrst_ctrl_ec_rst_l 1.232h 20.855ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_flash_wp_l chip_sw_sysrst_ctrl_ec_rst_l 1.232h 20.855ms 3 3 100.00
V2 chip_sw_sysrst_ctrl_ulp_z3_wakeup chip_sw_sysrst_ctrl_ulp_z3_wakeup 10.054m 5.367ms 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 11.199m 19.334ms 3 3 100.00
V2 chip_sw_edn_entropy_reqs chip_sw_csrng_edn_concurrency 1.638h 26.968ms 10 10 100.00
chip_sw_entropy_src_ast_rng_req 5.224m 2.994ms 3 3 100.00
chip_sw_edn_entropy_reqs 21.211m 6.334ms 3 3 100.00
V2 chip_sw_entropy_src_ast_rng_req chip_sw_entropy_src_ast_rng_req 5.224m 2.994ms 3 3 100.00
V2 chip_sw_entropy_src_csrng chip_sw_entropy_src_csrng 32.989m 7.970ms 3 3 100.00
V2 chip_sw_entropy_src_fuse_en_fw_read chip_sw_entropy_src_fuse_en_fw_read_test 0 0 --
V2 chip_sw_entropy_src_known_answer_tests chip_sw_entropy_src_kat_test 4.665m 2.693ms 3 3 100.00
V2 chip_sw_entropy_src_fw_observe_many_contiguous chip_sw_entropy_src_fw_observe_many_contiguous 0 0 --
V2 chip_sw_entropy_src_fw_extract_and_insert chip_sw_entropy_src_fw_extract_and_insert 0 0 --
V2 chip_sw_flash_init chip_sw_flash_init 38.999m 19.956ms 3 3 100.00
V2 chip_sw_flash_host_access chip_sw_flash_ctrl_access 22.570m 5.145ms 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 20.547m 5.729ms 3 3 100.00
V2 chip_sw_flash_ctrl_ops chip_sw_flash_ctrl_ops 10.971m 4.290ms 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 14.822m 4.097ms 3 3 100.00
V2 chip_sw_flash_rma_unlocked chip_sw_flash_rma_unlocked 1.606h 43.052ms 3 3 100.00
V2 chip_sw_flash_scramble chip_sw_flash_init 38.999m 19.956ms 3 3 100.00
V2 chip_sw_flash_idle_low_power chip_sw_flash_ctrl_idle_low_power 7.639m 3.555ms 3 3 100.00
V2 chip_sw_flash_keymgr_seeds chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
V2 chip_sw_flash_lc_creator_seed_sw_rw_en chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
V2 chip_sw_flash_creator_seed_wipe_on_rma chip_sw_flash_rma_unlocked 1.606h 43.052ms 3 3 100.00
V2 chip_sw_flash_lc_owner_seed_sw_rw_en chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
V2 chip_sw_flash_lc_iso_part_sw_rd_en chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
V2 chip_sw_flash_lc_iso_part_sw_wr_en chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
V2 chip_sw_flash_lc_seed_hw_rd_en chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
V2 chip_sw_flash_lc_escalate_en chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V2 chip_sw_flash_prim_tl_access chip_prim_tl_access 0 3 0.00
V2 chip_sw_flash_ctrl_clock_freqs chip_sw_flash_ctrl_clock_freqs 23.241m 5.803ms 3 3 100.00
V2 chip_sw_flash_ctrl_escalation_reset chip_sw_flash_crash_alert 13.920m 5.503ms 3 3 100.00
V2 chip_sw_flash_ctrl_write_clear chip_sw_flash_crash_alert 13.920m 5.503ms 3 3 100.00
V2 chip_sw_hmac_enc chip_sw_hmac_enc 5.071m 2.968ms 3 3 100.00
chip_sw_hmac_enc_jitter_en 5.810m 3.659ms 3 3 100.00
V2 chip_sw_hmac_idle chip_sw_hmac_enc_idle 5.566m 3.341ms 3 3 100.00
V2 chip_sw_hmac_all_configurations chip_sw_hmac_oneshot 7.461m 3.683ms 3 3 100.00
V2 chip_sw_hmac_multistream_mode chip_sw_hmac_multistream 37.991m 8.442ms 3 3 100.00
V2 chip_sw_i2c_host_tx_rx chip_sw_i2c_host_tx_rx 15.336m 5.340ms 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 16.581m 4.723ms 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 18.155m 5.905ms 3 3 100.00
V2 chip_sw_i2c_device_tx_rx chip_sw_i2c_device_tx_rx 11.898m 3.873ms 3 3 100.00
V2 chip_sw_keymgr_key_derivation chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 42.239m 12.623ms 3 3 100.00
V2 chip_sw_keymgr_sideload_kmac chip_sw_keymgr_sideload_kmac 45.215m 11.787ms 2 3 66.67
V2 chip_sw_keymgr_sideload_aes chip_sw_keymgr_sideload_aes 37.885m 10.821ms 3 3 100.00
V2 chip_sw_keymgr_sideload_otbn chip_sw_keymgr_sideload_otbn 1.406h 15.500ms 3 3 100.00
V2 chip_sw_kmac_enc chip_sw_kmac_mode_cshake 4.558m 3.140ms 3 3 100.00
chip_sw_kmac_mode_kmac 6.632m 3.321ms 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 6.175m 3.399ms 3 3 100.00
V2 chip_sw_kmac_app_keymgr chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
V2 chip_sw_kmac_app_lc chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_kmac_app_rom chip_sw_kmac_app_rom 4.643m 3.244ms 3 3 100.00
V2 chip_sw_kmac_entropy chip_sw_kmac_entropy 5.207m 2.971ms 3 3 100.00
V2 chip_sw_kmac_idle chip_sw_kmac_idle 5.266m 3.525ms 3 3 100.00
V2 chip_sw_lc_ctrl_alert_handler_escalation chip_sw_alert_handler_escalation 10.281m 5.457ms 3 3 100.00
V2 chip_sw_lc_ctrl_jtag_access chip_tap_straps_dev 25.658m 16.187ms 5 5 100.00
chip_tap_straps_rma 29.880m 14.990ms 4 5 80.00
chip_tap_straps_prod 30.627m 16.908ms 5 5 100.00
V2 chip_sw_lc_ctrl_otp_hw_cfg0 chip_sw_lc_ctrl_otp_hw_cfg0 5.112m 2.391ms 3 3 100.00
V2 chip_sw_lc_ctrl_init chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_lc_ctrl_transitions chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_lc_ctrl_kmac_req chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_lc_ctrl_key_div chip_sw_keymgr_key_derivation_prod 47.900m 11.768ms 3 3 100.00
V2 chip_sw_lc_ctrl_broadcast chip_sw_flash_ctrl_lc_rw_en 10.892m 5.477ms 3 3 100.00
chip_sw_flash_rma_unlocked 1.606h 43.052ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 11.808m 5.154ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 23.696m 9.394ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 27.026m 7.680ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 28.070m 8.854ms 3 3 100.00
chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
chip_sw_rom_ctrl_integrity_check 8.263m 9.670ms 3 3 100.00
chip_sw_sram_ctrl_execution_main 17.010m 8.442ms 3 3 100.00
chip_prim_tl_access 0 3 0.00
chip_sw_clkmgr_external_clk_src_for_lc 19.270m 12.461ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 15.075m 4.017ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 13.146m 4.153ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 9.994m 3.878ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 11.937m 5.139ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 12.405m 3.921ms 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 13.346m 4.330ms 3 3 100.00
chip_tap_straps_dev 25.658m 16.187ms 5 5 100.00
chip_tap_straps_rma 29.880m 14.990ms 4 5 80.00
chip_tap_straps_prod 30.627m 16.908ms 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
V2 chip_lc_scrap chip_sw_lc_ctrl_rma_to_scrap 4.901m 3.660ms 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 2.330m 2.601ms 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 2.288m 3.064ms 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 2.884m 3.909ms 3 3 100.00
V2 chip_lc_test_locked chip_sw_lc_walkthrough_testunlocks 43.329m 22.833ms 3 3 100.00
chip_rv_dm_lc_disabled 0 3 0.00
V2 chip_sw_lc_walkthrough chip_sw_lc_walkthrough_dev 1.718h 49.773ms 3 3 100.00
chip_sw_lc_walkthrough_prod 1.810h 48.059ms 3 3 100.00
chip_sw_lc_walkthrough_prodend 21.145m 8.174ms 3 3 100.00
chip_sw_lc_walkthrough_rma 1.567h 45.834ms 3 3 100.00
chip_sw_lc_walkthrough_testunlocks 43.329m 22.833ms 3 3 100.00
V2 chip_sw_lc_ctrl_volatile_raw_unlock chip_sw_lc_ctrl_volatile_raw_unlock 1.986m 2.365ms 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 2.058m 2.390ms 3 3 100.00
rom_volatile_raw_unlock 2.396m 2.827ms 3 3 100.00
V2 chip_otp_ctrl_init chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_otp_ctrl_keys chip_sw_flash_init 38.999m 19.956ms 3 3 100.00
chip_sw_otbn_mem_scramble 10.115m 3.574ms 3 3 100.00
chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 10.041m 3.768ms 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 4.617m 3.064ms 3 3 100.00
V2 chip_sw_otp_ctrl_entropy chip_sw_flash_init 38.999m 19.956ms 3 3 100.00
chip_sw_otbn_mem_scramble 10.115m 3.574ms 3 3 100.00
chip_sw_keymgr_key_derivation 45.475m 10.475ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 10.041m 3.768ms 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 4.617m 3.064ms 3 3 100.00
V2 chip_sw_otp_ctrl_program chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
V2 chip_sw_otp_ctrl_program_error chip_sw_lc_ctrl_program_error 11.046m 5.579ms 3 3 100.00
V2 chip_sw_otp_ctrl_hw_cfg0 chip_sw_lc_ctrl_otp_hw_cfg0 5.112m 2.391ms 3 3 100.00
V2 chip_sw_otp_ctrl_lc_signals chip_sw_otp_ctrl_lc_signals_test_unlocked0 11.808m 5.154ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 23.696m 9.394ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 27.026m 7.680ms 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 28.070m 8.854ms 3 3 100.00
chip_sw_lc_ctrl_transition 22.305m 10.581ms 15 15 100.00
chip_prim_tl_access 0 3 0.00
V2 chip_sw_otp_prim_tl_access chip_prim_tl_access 0 3 0.00
V2 chip_sw_otp_ctrl_dai_lock chip_sw_otp_ctrl_dai_lock 1.499h 28.935ms 1 1 100.00
V2 chip_sw_pwrmgr_external_full_reset chip_sw_pwrmgr_full_aon_reset 7.630m 7.822ms 3 3 100.00
V2 chip_sw_pwrmgr_random_sleep_all_wake_ups chip_sw_pwrmgr_random_sleep_all_wake_ups 33.627m 24.253ms 3 3 100.00
V2 chip_sw_pwrmgr_normal_sleep_all_wake_ups chip_sw_pwrmgr_normal_sleep_all_wake_ups 8.522m 6.909ms 3 3 100.00
V2 chip_sw_pwrmgr_deep_sleep_por_reset chip_sw_pwrmgr_deep_sleep_por_reset 14.616m 9.154ms 3 3 100.00
V2 chip_sw_pwrmgr_normal_sleep_por_reset chip_sw_pwrmgr_normal_sleep_por_reset 14.885m 7.679ms 3 3 100.00
V2 chip_sw_pwrmgr_deep_sleep_all_wake_ups chip_sw_pwrmgr_deep_sleep_all_wake_ups 34.849m 22.824ms 3 3 100.00
V2 chip_sw_pwrmgr_deep_sleep_all_reset_reqs chip_sw_pwrmgr_deep_sleep_all_reset_reqs 26.171m 14.819ms 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 13.284m 8.725ms 3 3 100.00
V2 chip_sw_pwrmgr_normal_sleep_all_reset_reqs chip_sw_pwrmgr_normal_sleep_all_reset_reqs 24.023m 12.153ms 3 3 100.00
V2 chip_sw_pwrmgr_wdog_reset chip_sw_pwrmgr_wdog_reset 9.744m 4.123ms 3 3 100.00
V2 chip_sw_pwrmgr_aon_power_glitch_reset chip_sw_pwrmgr_full_aon_reset 7.630m 7.822ms 3 3 100.00
V2 chip_sw_pwrmgr_main_power_glitch_reset chip_sw_pwrmgr_main_power_glitch_reset 9.292m 4.619ms 3 3 100.00
V2 chip_sw_pwrmgr_random_sleep_power_glitch_reset chip_sw_pwrmgr_random_sleep_power_glitch_reset 1.052h 39.038ms 3 3 100.00
V2 chip_sw_pwrmgr_deep_sleep_power_glitch_reset chip_sw_pwrmgr_deep_sleep_power_glitch_reset 8.928m 5.974ms 3 3 100.00
V2 chip_sw_pwrmgr_sleep_power_glitch_reset chip_sw_pwrmgr_sleep_power_glitch_reset 9.647m 5.245ms 3 3 100.00
V2 chip_sw_pwrmgr_random_sleep_all_reset_reqs chip_sw_pwrmgr_random_sleep_all_reset_reqs 51.963m 28.147ms 3 3 100.00
V2 chip_sw_pwrmgr_sysrst_ctrl_reset chip_sw_pwrmgr_sysrst_ctrl_reset 18.216m 7.951ms 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 30.055m 12.443ms 3 3 100.00
V2 chip_sw_pwrmgr_b2b_sleep_reset_req chip_sw_pwrmgr_b2b_sleep_reset_req 55.159m 31.189ms 3 3 100.00
V2 chip_sw_pwrmgr_sleep_disabled chip_sw_pwrmgr_sleep_disabled 5.704m 3.852ms 3 3 100.00
V2 chip_sw_pwrmgr_escalation_reset chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V2 chip_sw_rom_access chip_sw_rom_ctrl_integrity_check 8.263m 9.670ms 3 3 100.00
V2 chip_sw_rom_ctrl_integrity_check chip_sw_rom_ctrl_integrity_check 8.263m 9.670ms 3 3 100.00
V2 chip_sw_rstmgr_non_sys_reset_info chip_sw_pwrmgr_all_reset_reqs 30.055m 12.443ms 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 51.963m 28.147ms 3 3 100.00
chip_sw_pwrmgr_wdog_reset 9.744m 4.123ms 3 3 100.00
chip_sw_pwrmgr_smoketest 8.826m 6.803ms 3 3 100.00
V2 chip_sw_rstmgr_sys_reset_info chip_rv_dm_ndm_reset_req 9.478m 3.744ms 3 3 100.00
V2 chip_sw_rstmgr_cpu_info chip_sw_rstmgr_cpu_info 13.452m 7.091ms 3 3 100.00
V2 chip_sw_rstmgr_sw_req_reset chip_sw_rstmgr_sw_req 9.634m 3.649ms 3 3 100.00
V2 chip_sw_rstmgr_alert_info chip_sw_rstmgr_alert_info 34.008m 12.090ms 3 3 100.00
V2 chip_sw_rstmgr_sw_rst chip_sw_rstmgr_sw_rst 5.732m 3.389ms 3 3 100.00
V2 chip_sw_rstmgr_escalation_reset chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V2 chip_sw_rstmgr_alert_handler_reset_enables chip_sw_alert_handler_lpg_reset_toggle 30.773m 8.186ms 3 3 100.00
V2 chip_sw_plic_all_irqs chip_plic_all_irqs_0 23.160m 5.539ms 3 3 100.00
chip_plic_all_irqs_10 11.946m 4.007ms 3 3 100.00
chip_plic_all_irqs_20 14.318m 4.690ms 3 3 100.00
V2 chip_sw_plic_sw_irq chip_sw_plic_sw_irq 6.038m 2.776ms 3 3 100.00
V2 chip_sw_timer chip_sw_rv_timer_irq 5.097m 3.062ms 3 3 100.00
V2 chip_sw_spi_device_flash_mode rom_e2e_smoke 1.238h 14.768ms 3 3 100.00
V2 chip_sw_spi_device_pass_through chip_sw_spi_device_pass_through 15.396m 7.384ms 3 3 100.00
V2 chip_sw_spi_device_pass_through_collision chip_sw_spi_device_pass_through_collision 10.602m 4.425ms 3 3 100.00
V2 chip_sw_spi_device_tpm chip_sw_spi_device_tpm 7.387m 3.865ms 3 3 100.00
V2 chip_sw_spi_host_tx_rx chip_sw_spi_host_tx_rx 6.018m 2.601ms 3 3 100.00
V2 chip_sw_sram_scrambled_access chip_sw_sram_ctrl_scrambled_access 10.041m 3.768ms 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 13.051m 5.773ms 3 3 100.00
V2 chip_sw_sleep_sram_ret_contents chip_sw_sleep_sram_ret_contents_no_scramble 15.064m 6.975ms 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 16.319m 9.168ms 3 3 100.00
V2 chip_sw_sram_execution chip_sw_sram_ctrl_execution_main 17.010m 8.442ms 3 3 100.00
V2 chip_sw_sram_lc_escalation chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
chip_sw_data_integrity_escalation 14.589m 4.544ms 6 6 100.00
V2 chip_sw_usbdev_mem chip_sw_usbdev_mem 0 0 --
V2 chip_sw_usbdev_vbus chip_sw_usbdev_vbus 2.915m 2.235ms 1 1 100.00
V2 chip_sw_usbdev_pullup chip_sw_usbdev_pullup 5.770m 3.385ms 1 1 100.00
V2 chip_sw_usbdev_aon_pullup chip_sw_usbdev_aon_pullup 9.825m 4.263ms 1 1 100.00
V2 chip_sw_usbdev_sof chip_sw_usbdev_sof 0 0 --
V2 chip_sw_usbdev_setup_rx chip_sw_usbdev_setuprx 11.815m 3.348ms 1 1 100.00
V2 chip_sw_usbdev_config_host chip_sw_usbdev_config_host 39.543m 7.992ms 1 1 100.00
V2 chip_sw_usbdev_pincfg chip_sw_usbdev_pincfg 1.898h 31.952ms 1 1 100.00
V2 chip_sw_usbdev_tx_rx chip_sw_usbdev_dpi 52.076m 12.112ms 1 1 100.00
V2 chip_sw_alert_handler_alerts chip_sw_alert_test 6.585m 3.082ms 3 3 100.00
V2 chip_sw_alert_handler_escalations chip_sw_alert_handler_escalation 10.281m 5.457ms 3 3 100.00
V2 chip_sw_alert_handler_escalation_nmi_reset chip_sw_alert_handler_escalation_nmi_reset 0 0 --
V2 chip_sw_alert_handler_escalation_methods chip_sw_alert_handler_escalation_methods 0 0 --
V2 chip_sw_all_escalation_resets chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V2 chip_sw_alert_handler_irqs chip_plic_all_irqs 0 0 --
V2 chip_sw_alert_handler_entropy chip_sw_alert_handler_entropy 5.819m 3.518ms 3 3 100.00
V2 chip_sw_alert_handler_crashdump chip_sw_rstmgr_alert_info 34.008m 12.090ms 3 3 100.00
V2 chip_sw_alert_handler_ping_timeout chip_sw_alert_handler_ping_timeout 7.676m 4.220ms 3 3 100.00
V2 chip_sw_alert_handler_lpg_sleep_mode_alerts chip_sw_alert_handler_lpg_sleep_mode_alerts 10.226m 3.647ms 90 90 100.00
V2 chip_sw_alert_handler_lpg_sleep_mode_pings chip_sw_alert_handler_lpg_sleep_mode_pings 28.824m 11.928ms 3 3 100.00
V2 chip_sw_alert_handler_lpg_clock_off chip_sw_alert_handler_lpg_clkoff 36.101m 8.380ms 3 3 100.00
V2 chip_sw_alert_handler_lpg_reset_toggle chip_sw_alert_handler_lpg_reset_toggle 30.773m 8.186ms 3 3 100.00
V2 chip_sw_alert_handler_ping_ok chip_sw_alert_handler_ping_ok 23.812m 7.326ms 3 3 100.00
V2 chip_sw_alert_handler_reverse_ping_in_deep_sleep chip_sw_alert_handler_reverse_ping_in_deep_sleep 3.789h 254.862ms 2 3 66.67
V2 chip_jtag_csr_rw chip_jtag_csr_rw 33.855m 18.568ms 3 3 100.00
V2 chip_jtag_mem_access chip_jtag_mem_access 27.569m 13.057ms 3 3 100.00
V2 chip_rv_dm_ndm_reset_req chip_rv_dm_ndm_reset_req 9.478m 3.744ms 3 3 100.00
V2 chip_sw_rv_dm_ndm_reset_req_when_cpu_halted chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 9.975m 4.698ms 3 3 100.00
V2 chip_rv_dm_access_after_wakeup chip_sw_rv_dm_access_after_wakeup 10.572m 4.270ms 0 3 0.00
V2 chip_sw_rv_dm_jtag_tap_sel chip_tap_straps_rma 29.880m 14.990ms 4 5 80.00
V2 chip_rv_dm_lc_disabled chip_rv_dm_lc_disabled 0 3 0.00
V2 chip_rv_dm_jtag chip_rv_dm_jtag 0 0 --
V2 chip_rv_dm_dtm chip_rv_dm_dtm 0 0 --
V2 chip_rv_dm_control_status chip_rv_dm_control_status 0 0 --
V2 TOTAL 856 2644 32.38
V2S chip_sw_aes_masking_off chip_sw_aes_masking_off 6.684m 3.182ms 3 3 100.00
V2S TOTAL 3 3 100.00
V3 chip_sw_usb_suspend chip_sw_usb_suspend 0 0 --
V3 chip_usb_wake_debug chip_usb_wake_debug 0 0 --
V3 chip_sw_coremark chip_sw_coremark 0 1 0.00
V3 chip_sw_power_max_load chip_sw_power_virus 0 3 0.00
V3 rom_e2e_debug rom_e2e_jtag_debug_test_unlocked0 12.005m 7.878ms 0 1 0.00
rom_e2e_jtag_debug_dev 20.576m 6.801ms 0 1 0.00
rom_e2e_jtag_debug_rma 18.858m 7.321ms 0 1 0.00
V3 rom_e2e_jtag_inject rom_e2e_jtag_inject_test_unlocked0 48.979m 32.166ms 1 1 100.00
rom_e2e_jtag_inject_dev 53.881m 24.045ms 1 1 100.00
rom_e2e_jtag_inject_rma 37.537m 32.779ms 1 1 100.00
V3 rom_bootstrap_rma rom_bootstrap_rma 0 0 --
V3 rom_e2e_weak_straps rom_e2e_weak_straps 0 0 --
V3 rom_e2e_self_hash rom_e2e_self_hash 0 0 --
V3 manuf_cp_unlock_raw manuf_cp_unlock_raw 0 0 --
V3 manuf_scrap manuf_scrap 0 0 --
V3 manuf_cp_yield_test manuf_cp_yield_test 0 0 --
V3 manuf_cp_ast_test_execution manuf_cp_ast_test_execution 0 0 --
V3 manuf_cp_device_info_flash_wr manuf_cp_device_info_flash_wr 0 0 --
V3 manuf_cp_test_lock manuf_cp_test_lock 0 0 --
V3 manuf_ft_exit_token manuf_ft_exit_token 0 0 --
V3 manuf_ft_sku_individualization_preop manuf_ft_sku_individualization_preop 0 0 --
V3 manuf_ft_sku_individualization manuf_ft_sku_individualization 0 0 --
V3 manuf_ft_provision_rma_token_and_personalization manuf_ft_provision_rma_token_and_personalization 0 0 --
V3 manuf_ft_load_transport_image manuf_ft_load_transport_image 0 0 --
V3 manuf_ft_load_certificates manuf_ft_load_certificates 0 0 --
V3 manuf_ft_eom manuf_ft_eom 0 0 --
V3 manuf_rma_entry manuf_rma_entry 0 0 --
V3 manuf_sram_program_crc_functest manuf_sram_program_crc_functest 0 0 --
V3 chip_sw_adc_ctrl_normal chip_sw_adc_ctrl_normal 0 0 --
V3 chip_sw_adc_ctrl_oneshot chip_sw_adc_ctrl_oneshot 0 0 --
V3 chip_sw_clkmgr_jitter_cycle_measurements chip_sw_clkmgr_jitter_frequency 6.908m 3.828ms 3 3 100.00
V3 chip_sw_edn_boot_mode chip_sw_edn_boot_mode 12.216m 3.497ms 3 3 100.00
V3 chip_sw_edn_auto_mode chip_sw_edn_auto_mode 22.089m 4.512ms 3 3 100.00
V3 chip_sw_edn_sw_mode chip_sw_edn_sw_mode 22.568m 8.617ms 3 3 100.00
V3 chip_sw_edn_kat chip_sw_edn_kat 12.548m 3.593ms 3 3 100.00
V3 chip_sw_entropy_src_bypass_mode_health_tests chip_sw_entropy_src_bypass_mode_health_tests 0 0 --
V3 chip_sw_entropy_src_fips_mode_health_tests chip_sw_entropy_src_fips_mode_health_tests 0 0 --
V3 chip_sw_entropy_src_validation chip_sw_entropy_src_validation 0 0 --
V3 chip_sw_flash_memory_protection chip_sw_flash_ctrl_mem_protection 24.441m 5.548ms 3 3 100.00
V3 chip_sw_hmac_sha2_stress chip_sw_hmac_sha2_stress 0 0 --
V3 chip_sw_hmac_stress chip_sw_hmac_stress 0 0 --
V3 chip_sw_hmac_endianness chip_sw_hmac_endianness 0 0 --
V3 chip_sw_hmac_secure_wipe chip_sw_hmac_secure_wipe 0 0 --
V3 chip_sw_hmac_error_conditions chip_sw_hmac_error_conditions 0 0 --
V3 chip_sw_i2c_speed chip_sw_i2c_speed 0 0 --
V3 chip_sw_i2c_override //sw/device/tests:i2c_host_override_test 0 0 --
V3 chip_sw_i2c_clockstretching chip_sw_i2c_clockstretching 0 0 --
V3 chip_sw_i2c_nack chip_sw_i2c_nack 0 0 --
V3 chip_sw_i2c_repeatedstart chip_sw_i2c_repeatedstart 0 0 --
V3 chip_sw_keymgr_sideload_kmac_error chip_sw_keymgr_sideload_kmac_error 0 0 --
V3 chip_sw_keymgr_derive_attestation chip_sw_keymgr_derive_attestation 0 0 --
V3 chip_sw_keymgr_derive_sealing chip_sw_keymgr_derive_sealing 0 0 --
V3 chip_sw_kmac_sha3_stress chip_sw_kmac_sha3_stress 0 0 --
V3 chip_sw_kmac_shake_stress chip_sw_kmac_shake_stress 0 0 --
V3 chip_sw_kmac_cshake_stress chip_sw_kmac_cshake_stress 0 0 --
V3 chip_sw_kmac_kmac_stress chip_sw_kmac_kmac_stress 0 0 --
V3 chip_sw_kmac_kmac_key_sideload chip_sw_kmac_kmac_key_sideload 0 0 --
V3 chip_sw_kmac_endianess chip_sw_kmac_endianess 0 0 --
V3 chip_sw_kmac_entropy_stress chip_sw_kmac_entropy_stress 0 0 --
V3 chip_sw_kmac_error_conditions chip_sw_kmac_error_conditions 0 0 --
V3 chip_sw_lc_ctrl_kmac_error chip_sw_lc_ctrl_kmac_error 0 0 --
V3 chip_sw_lc_ctrl_debug_access chip_sw_lc_ctrl_debug_access 0 0 --
V3 chip_sw_otp_ctrl_vendor_test_csr_access chip_sw_otp_ctrl_vendor_test_csr_access 5.094m 3.241ms 3 3 100.00
V3 chip_sw_otp_ctrl_escalation chip_sw_otp_ctrl_escalation 9.429m 4.211ms 1 1 100.00
V3 otp_ctrl_calibration otp_ctrl_calibration 0 0 --
V3 otp_ctrl_partition_access_locked otp_ctrl_partition_access_locked 0 0 --
V3 otp_ctrl_check_timeout otp_ctrl_check_timeout 0 0 --
V3 chip_sw_sensor_ctrl_deep_sleep_wake_up chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 10.232m 5.970ms 3 3 100.00
V3 chip_sw_pwrmgr_usb_clk_disabled_when_active chip_sw_pwrmgr_usb_clk_disabled_when_active 8.902m 4.719ms 3 3 100.00
V3 chip_sw_all_resets chip_sw_pwrmgr_all_reset_reqs 30.055m 12.443ms 3 3 100.00
V3 chip_sw_rom_ctrl_kmac_error chip_sw_rom_ctrl_kmac_error 0 0 --
V3 chip_sw_rom_ctrl_digests chip_sw_rom_ctrl_digests 0 0 --
V3 chip_sw_plic_alerts chip_sw_all_escalation_resets 15.697m 4.995ms 98 100 98.00
V3 tick_configuration chip_sw_rv_timer_systick_test 0 3 0.00
V3 counter_wrap chip_sw_rv_timer_systick_test 0 3 0.00
V3 chip_sw_spi_device_pass_through_flash_model //sw/device/tests:spi_passthru_test 0 0 --
V3 chip_sw_spi_device_output_when_disabled_or_sleeping chip_sw_spi_device_output_when_disabled_or_sleeping 0 0 --
V3 chip_sw_spi_host_pass_through //sw/device/tests:spi_passthru_test 0 0 --
V3 chip_sw_spi_host_configuration chip_sw_spi_host_configuration 0 0 --
V3 chip_sw_spi_host_events chip_sw_spi_host_events 0 0 --
V3 chip_sw_sram_memset chip_sw_sram_memset 0 0 --
V3 chip_sw_sram_subword_access chip_sw_sram_subword_access 0 0 --
V3 chip_sw_uart_parity chip_sw_uart_parity 0 0 --
V3 chip_sw_uart_line_loopback chip_sw_uart_line_loopback 0 0 --
V3 chip_sw_uart_system_loopback chip_sw_uart_system_loopback 0 0 --
V3 chip_sw_uart_line_break chip_sw_uart_line_break 0 0 --
V3 chip_sw_uart_watermarks chip_sw_uart_tx_rx 11.861m 4.174ms 5 5 100.00
V3 chip_sw_usbdev_stream chip_sw_usbdev_stream 1.404h 18.406ms 1 1 100.00
V3 chip_sw_usbdev_iso chip_sw_usbdev_iso 0 0 --
V3 chip_sw_usbdev_mixed chip_sw_usbdev_mixed 0 0 --
V3 chip_sw_usbdev_suspend_resume chip_sw_usbdev_suspend_resume 0 0 --
V3 chip_sw_usbdev_aon_wake_reset chip_sw_usbdev_aon_wake_reset 0 0 --
V3 chip_sw_usbdev_aon_wake_disconnect chip_sw_usbdev_aon_wake_disconnect 0 0 --
V3 chip_sw_usbdev_toggle_restore chip_sw_usbdev_toggle_restore 0 0 --
V3 chip_rv_dm_perform_debug rom_e2e_jtag_debug_test_unlocked0 12.005m 7.878ms 0 1 0.00
rom_e2e_jtag_debug_dev 20.576m 6.801ms 0 1 0.00
rom_e2e_jtag_debug_rma 18.858m 7.321ms 0 1 0.00
V3 chip_sw_rv_dm_access_after_hw_reset chip_sw_rv_dm_access_after_escalation_reset 11.269m 5.900ms 3 3 100.00
V3 TOTAL 35 45 77.78
Unmapped tests chip_sival_flash_info_access 5.689m 3.170ms 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 10.396m 5.914ms 3 3 100.00
chip_sw_otp_ctrl_ecc_error_vendor_test 6.668m 3.488ms 3 3 100.00
chip_sw_otbn_ecdsa_op_irq 1.324h 17.798ms 3 3 100.00
chip_sw_rv_core_ibex_rnd 18.082m 5.487ms 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 15.984m 5.345ms 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 9.662m 4.156ms 3 3 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.989m 6.616ms 3 3 100.00
chip_sw_rv_core_ibex_address_translation 5.376m 3.293ms 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 3.088m 2.537ms 3 3 100.00
chip_sw_flash_ctrl_write_clear 7.189m 3.356ms 3 3 100.00
TOTAL 992 2945 33.68

Testplan Progress

Items Total Written Passing Progress
N.A. 11 11 11 100.00
V1 18 18 12 66.67
V2 285 270 225 78.95
V2S 1 1 1 100.00
V3 90 21 15 16.67

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
86.33 90.77 80.03 90.28 -- 92.11 81.66 83.11

Failure Buckets

Past Results