Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3908437	1			T75	8422		T76	6		T77	34
values[2]	779480	1			T75	1717		T76	6		T77	109
values[3]	114273	1			T75	158		T76	6		T77	64
values[4]	61566	1			T75	120		T76	6		T77	33
values[5]	41768	1			T75	110		T76	6		T77	16
values[6]	32139	1			T75	96		T76	6		T77	1
values[7]	25880	1			T75	92		T76	6		T156	137
values[8]	22609	1			T75	97		T76	6		T156	115
values[9]	19941	1			T75	94		T76	6		T156	107
values[10]	17975	1			T75	85		T76	7		T156	92
values[11]	16974	1			T75	63		T76	6		T156	66
values[12]	15792	1			T75	76		T76	6		T156	70
values[13]	14785	1			T75	82		T76	6		T156	76
values[14]	14213	1			T75	104		T76	6		T156	66
values[15]	13764	1			T75	97		T76	6		T156	80
values[16]	13272	1			T75	113		T76	6		T156	88
values[17]	12749	1			T75	84		T76	6		T156	46
values[18]	11904	1			T75	79		T76	6		T156	41
values[19]	11769	1			T75	110		T76	6		T156	47
values[20]	11511	1			T75	85		T76	6		T156	41
values[21]	10936	1			T75	107		T76	6		T156	30
values[22]	10805	1			T75	93		T76	6		T156	31
values[23]	10490	1			T75	82		T76	6		T156	28
values[24]	10128	1			T75	88		T76	6		T156	24
values[25]	9506	1			T75	99		T76	6		T156	27
values[26]	9385	1			T75	74		T76	6		T156	53
values[27]	8884	1			T75	62		T76	6		T156	57
values[28]	8383	1			T75	56		T76	6		T156	42
values[29]	8005	1			T75	61		T76	6		T156	23
values[30]	7196	1			T75	57		T76	6		T156	38
values[31]	6477	1			T75	48		T76	6		T156	48
values[32]	6347	1			T75	31		T76	6		T156	43
values[33]	5702	1			T75	18		T76	6		T156	50
values[34]	5382	1			T75	17		T76	6		T156	46
values[35]	5232	1			T75	17		T76	6		T156	29
values[36]	4895	1			T75	20		T76	6		T156	36
values[37]	4555	1			T75	13		T76	6		T156	45
values[38]	4385	1			T75	22		T76	6		T156	58
values[39]	4079	1			T75	8		T76	6		T156	44
values[40]	3808	1			T75	10		T76	6		T156	18
values[41]	3706	1			T75	7		T76	6		T156	15
values[42]	3613	1			T75	16		T76	6		T156	31
values[43]	3479	1			T75	9		T76	7		T156	19
values[44]	3388	1			T75	5		T76	6		T156	15
values[45]	3245	1			T75	5		T76	6		T156	9
values[46]	3249	1			T75	4		T76	6		T156	5
values[47]	3155	1			T75	1		T76	6		T156	5
values[48]	3076	1			T75	1		T76	6		T156	5
values[49]	3050	1			T75	3		T76	6		T156	5
values[50]	2945	1			T75	5		T76	7		T156	5
values[51]	2804	1			T75	2		T76	6		T156	4
values[52]	2826	1			T75	4		T76	6		T156	4
values[53]	2883	1			T75	2		T76	6		T156	3
values[54]	2776	1			T75	1		T76	6		T156	4
values[55]	2677	1			T75	1		T76	6		T156	6
values[56]	2640	1			T76	7		T156	7		T131	13
values[57]	2678	1			T76	6		T156	7		T131	13
values[58]	2628	1			T76	6		T156	4		T131	13
values[59]	2611	1			T76	6		T156	7		T131	14
values[60]	2538	1			T76	6		T156	5		T131	13
values[61]	2753	1			T76	6		T156	4		T131	13
values[62]	4200	1			T76	6		T156	17		T131	13
values[63]	11915	1			T76	7		T156	67		T131	14
values[64]	238931	1			T76	1081		T156	239		T131	2433

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5013853	1			T75	11077		T76	999		T77	171
values[2]	850120	1			T75	2224		T76	304		T77	45
values[3]	87532	1			T75	56		T76	99		T77	4
values[4]	15428	1			T75	5		T76	32		T156	10
values[5]	6020	1			T76	12		T156	1		T131	19
values[6]	3885	1			T76	4		T131	7		T547	1
values[7]	2923	1			T76	1		T131	4		T547	1
values[8]	2429	1			T131	3		T546	7		T545	58
values[9]	2076	1			T131	2		T546	5		T545	47
values[10]	1712	1			T131	2		T546	5		T545	37
values[11]	1556	1			T131	2		T546	5		T545	23
values[12]	1419	1			T131	2		T546	6		T545	34
values[13]	1428	1			T131	2		T546	5		T545	36
values[14]	1256	1			T131	2		T546	5		T545	58
values[15]	1140	1			T131	2		T546	5		T545	45
values[16]	1076	1			T131	2		T546	5		T545	32
values[17]	1089	1			T131	2		T546	5		T545	28
values[18]	892	1			T131	2		T546	5		T545	22
values[19]	920	1			T131	2		T546	5		T545	36
values[20]	872	1			T131	2		T546	5		T545	34
values[21]	842	1			T131	2		T546	5		T545	30
values[22]	768	1			T131	2		T546	5		T545	21
values[23]	740	1			T131	2		T546	5		T545	14
values[24]	732	1			T131	2		T546	5		T545	19
values[25]	693	1			T131	2		T546	5		T545	16
values[26]	672	1			T131	2		T546	5		T545	10
values[27]	710	1			T131	2		T546	5		T545	7
values[28]	676	1			T131	2		T546	5		T545	6
values[29]	618	1			T131	2		T546	5		T545	6
values[30]	617	1			T131	2		T546	5		T545	11
values[31]	627	1			T131	2		T546	5		T545	14
values[32]	604	1			T131	2		T546	5		T545	4
values[33]	548	1			T131	2		T546	5		T545	7
values[34]	572	1			T131	2		T546	5		T545	2
values[35]	585	1			T131	2		T546	5		T545	5
values[36]	582	1			T131	2		T546	5		T545	2
values[37]	551	1			T131	2		T546	5		T545	2
values[38]	536	1			T131	2		T546	5		T545	2
values[39]	575	1			T131	2		T546	5		T545	7
values[40]	494	1			T131	2		T546	5		T545	5
values[41]	470	1			T131	2		T546	5		T545	5
values[42]	475	1			T131	2		T546	5		T545	4
values[43]	461	1			T131	2		T546	5		T545	7
values[44]	472	1			T131	2		T546	5		T545	4
values[45]	444	1			T131	2		T546	5		T545	8
values[46]	452	1			T131	2		T546	5		T545	11
values[47]	457	1			T131	2		T546	5		T545	10
values[48]	447	1			T131	2		T546	5		T545	8
values[49]	449	1			T131	2		T546	5		T545	4
values[50]	443	1			T131	2		T546	5		T545	2
values[51]	454	1			T131	2		T546	5		T545	7
values[52]	462	1			T131	2		T546	6		T545	7
values[53]	479	1			T131	2		T546	5		T545	7
values[54]	452	1			T131	2		T546	5		T545	9
values[55]	398	1			T131	2		T546	6		T545	6
values[56]	398	1			T131	2		T546	5		T545	4
values[57]	364	1			T131	2		T546	5		T545	5
values[58]	366	1			T131	2		T546	5		T545	4
values[59]	390	1			T131	2		T546	5		T545	6
values[60]	388	1			T131	2		T546	5		T545	6
values[61]	443	1			T131	2		T546	5		T545	8
values[62]	684	1			T131	2		T546	5		T545	23
values[63]	2627	1			T131	4		T546	6		T545	76
values[64]	28609	1			T131	362		T546	917		T545	95

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	592199	1			T75	336		T76	6		T77	1
values[2]	2828851	1			T75	8822		T76	7		T77	38
values[3]	1198442	1			T75	1602		T76	6		T77	83
values[4]	160283	1			T75	102		T76	6		T77	33
values[5]	83867	1			T75	105		T76	6		T77	31
values[6]	55103	1			T75	103		T76	6		T77	19
values[7]	40147	1			T75	77		T76	6		T77	10
values[8]	31418	1			T75	86		T76	6		T156	191
values[9]	26442	1			T75	75		T76	6		T156	113
values[10]	23896	1			T75	122		T76	6		T156	76
values[11]	21744	1			T75	124		T76	6		T156	72
values[12]	20332	1			T75	110		T76	6		T156	114
values[13]	19165	1			T75	103		T76	7		T156	120
values[14]	18106	1			T75	94		T76	6		T156	102
values[15]	16908	1			T75	97		T76	6		T156	67
values[16]	16083	1			T75	105		T76	6		T156	55
values[17]	15457	1			T75	99		T76	6		T156	63
values[18]	14738	1			T75	96		T76	6		T156	42
values[19]	14479	1			T75	107		T76	6		T156	38
values[20]	13687	1			T75	80		T76	6		T156	51
values[21]	12981	1			T75	84		T76	6		T156	58
values[22]	12428	1			T75	95		T76	7		T156	64
values[23]	11664	1			T75	72		T76	6		T156	60
values[24]	11523	1			T75	67		T76	6		T156	41
values[25]	11178	1			T75	60		T76	6		T156	50
values[26]	10589	1			T75	73		T76	6		T156	61
values[27]	10046	1			T75	61		T76	6		T156	60
values[28]	9689	1			T75	59		T76	6		T156	54
values[29]	8929	1			T75	62		T76	6		T156	62
values[30]	8175	1			T75	77		T76	6		T156	37
values[31]	7497	1			T75	86		T76	6		T156	29
values[32]	6973	1			T75	62		T76	6		T156	17
values[33]	6390	1			T75	29		T76	6		T156	22
values[34]	5852	1			T75	16		T76	6		T156	25
values[35]	5400	1			T75	16		T76	6		T156	37
values[36]	5017	1			T75	9		T76	6		T156	31
values[37]	4790	1			T75	8		T76	6		T156	25
values[38]	4621	1			T75	13		T76	6		T156	28
values[39]	4439	1			T75	8		T76	6		T156	20
values[40]	4219	1			T75	6		T76	6		T156	12
values[41]	4052	1			T75	10		T76	6		T156	5
values[42]	3899	1			T75	7		T76	6		T156	6
values[43]	3852	1			T75	7		T76	6		T156	9
values[44]	3737	1			T75	6		T76	6		T156	5
values[45]	3688	1			T75	11		T76	6		T156	5
values[46]	3730	1			T75	7		T76	6		T156	7
values[47]	3579	1			T75	13		T76	6		T156	6
values[48]	3623	1			T75	12		T76	6		T156	4
values[49]	3457	1			T75	8		T76	6		T156	6
values[50]	3388	1			T75	6		T76	7		T156	12
values[51]	3300	1			T75	6		T76	7		T156	6
values[52]	3269	1			T75	4		T76	6		T156	6
values[53]	3238	1			T75	1		T76	6		T156	17
values[54]	3221	1			T75	2		T76	6		T156	13
values[55]	3119	1			T76	6		T156	4		T131	15
values[56]	3067	1			T76	6		T156	6		T131	13
values[57]	3117	1			T76	6		T156	9		T131	13
values[58]	3014	1			T76	6		T156	10		T131	13
values[59]	2855	1			T76	6		T156	7		T131	13
values[60]	2892	1			T76	6		T156	4		T131	13
values[61]	2980	1			T76	6		T156	7		T131	13
values[62]	3860	1			T76	6		T156	14		T131	13
values[63]	10007	1			T76	6		T156	44		T131	25
values[64]	225629	1			T76	1141		T156	128		T131	2414