Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2166652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37166909

1

T4

5264

T5

14479

T6

7851

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27542113	1			T4	2036		T5	6281		T6	2310
values[0x0]	10339348	1			T4	3228		T5	8198		T6	5541
values[0x1]	1452100	1			T4	275		T5	1084		T6	308

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	754259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38579302

1

T4

5539

T5

15563

T6

8159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18382392	1			T4	2770		T5	7782		T6	4080
valid_sources[0x01]	18382124	1			T4	2769		T5	7781		T6	4079
valid_sources[0x02]	40705	1			T130	56		T544	26		T150	352
valid_sources[0x03]	41177	1			T149	2		T130	61		T544	21
valid_sources[0x04]	41272	1			T149	2		T130	37		T544	11
valid_sources[0x05]	42063	1			T149	1		T213	1		T130	56
valid_sources[0x06]	41972	1			T78	1		T149	1		T213	1
valid_sources[0x07]	40775	1			T213	1		T130	57		T544	39
valid_sources[0x08]	42401	1			T78	8		T213	3		T130	46
valid_sources[0x09]	41008	1			T213	1		T130	52		T544	20
valid_sources[0x0a]	42227	1			T213	1		T130	68		T544	21
valid_sources[0x0b]	42164	1			T78	2		T213	2		T130	55
valid_sources[0x0c]	41300	1			T213	2		T130	45		T544	34
valid_sources[0x0d]	40619	1			T130	69		T544	24		T150	380
valid_sources[0x0e]	40572	1			T78	5		T8	8		T130	73
valid_sources[0x0f]	41609	1			T78	1		T213	1		T130	42
valid_sources[0x10]	41948	1			T78	1		T130	78		T544	25
valid_sources[0x11]	40561	1			T78	2		T130	65		T544	18
valid_sources[0x12]	41746	1			T130	62		T544	27		T150	420
valid_sources[0x13]	41103	1			T149	2		T130	74		T544	19
valid_sources[0x14]	40852	1			T130	90		T544	35		T150	365
valid_sources[0x15]	40949	1			T213	2		T130	62		T544	17
valid_sources[0x16]	40767	1			T78	4		T130	51		T544	20
valid_sources[0x17]	41094	1			T8	12		T149	3		T212	39
valid_sources[0x18]	41764	1			T130	68		T544	28		T150	393
valid_sources[0x19]	42292	1			T78	1		T130	69		T544	30
valid_sources[0x1a]	40636	1			T149	1		T213	1		T130	49
valid_sources[0x1b]	40387	1			T130	67		T544	23		T150	400
valid_sources[0x1c]	41226	1			T130	108		T544	16		T150	395
valid_sources[0x1d]	40651	1			T79	39		T213	1		T130	68
valid_sources[0x1e]	42335	1			T149	2		T130	48		T544	16
valid_sources[0x1f]	41066	1			T130	76		T544	25		T150	476
valid_sources[0x20]	40970	1			T78	1		T213	2		T130	78

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26655268

1

T4

2036

T5

6281

T6

2310

values[0x0]

all_enables

biggest_size

10298200

1

T4

3228

T5

8198

T6

5541

values[0x1]

all_enables

biggest_size

213441

1

T78

23

T79

25

T8

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3039205	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

480137

1

T75

57

T76

204

T77

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1192076	1			T75	298		T76	503		T77	85
values[0x0]	1135745	1			T75	49		T76	499		T77	83
values[0x1]	1191521	1			T75	257		T76	462		T77	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2352722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1166620

1

T75

231

T76

496

T77

86

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55677	1			T75	9		T76	23		T156	64
valid_sources[0x01]	55252	1			T75	12		T76	17		T80	1
valid_sources[0x02]	56012	1			T75	10		T76	16		T77	3
valid_sources[0x03]	54407	1			T75	9		T76	17		T77	7
valid_sources[0x04]	54104	1			T75	7		T76	34		T77	1
valid_sources[0x05]	55719	1			T75	6		T76	21		T77	7
valid_sources[0x06]	54268	1			T75	8		T76	21		T77	3
valid_sources[0x07]	54402	1			T75	9		T76	34		T80	1
valid_sources[0x08]	55626	1			T75	9		T76	21		T77	2
valid_sources[0x09]	55115	1			T75	14		T76	21		T77	5
valid_sources[0x0a]	55811	1			T75	13		T76	24		T80	3
valid_sources[0x0b]	55859	1			T75	9		T76	24		T80	1
valid_sources[0x0c]	54046	1			T75	10		T76	22		T77	11
valid_sources[0x0d]	55296	1			T75	8		T76	20		T77	3
valid_sources[0x0e]	54802	1			T75	12		T76	20		T80	3
valid_sources[0x0f]	54501	1			T75	14		T76	21		T156	70
valid_sources[0x10]	54067	1			T75	10		T76	24		T80	2
valid_sources[0x11]	55418	1			T75	12		T76	21		T77	6
valid_sources[0x12]	55316	1			T75	10		T76	17		T77	1
valid_sources[0x13]	54783	1			T75	8		T76	24		T77	1
valid_sources[0x14]	55585	1			T75	8		T76	20		T77	1
valid_sources[0x15]	54797	1			T75	8		T76	28		T77	1
valid_sources[0x16]	54888	1			T75	12		T76	21		T77	4
valid_sources[0x17]	54516	1			T75	7		T76	20		T77	4
valid_sources[0x18]	55079	1			T75	13		T76	19		T77	1
valid_sources[0x19]	55495	1			T75	7		T76	21		T77	5
valid_sources[0x1a]	53510	1			T75	14		T76	20		T77	5
valid_sources[0x1b]	55228	1			T75	9		T76	28		T77	8
valid_sources[0x1c]	54835	1			T75	11		T76	26		T77	3
valid_sources[0x1d]	55591	1			T75	7		T76	24		T77	10
valid_sources[0x1e]	54898	1			T75	4		T76	12		T77	7
valid_sources[0x1f]	55485	1			T75	12		T76	23		T77	2
valid_sources[0x20]	56081	1			T75	11		T76	22		T77	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50008

1

T75

24

T76

18

T77

2

values[0x0]

all_enables

biggest_size

379451

1

T75

18

T76

173

T77

25

values[0x1]

all_enables

biggest_size

50678

1

T75

15

T76

13

T77

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3229517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

524999

1

T75

72

T76

210

T77

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1285943	1			T75	279		T76	512		T77	79
values[0x0]	1183608	1			T75	43		T76	460		T77	65
values[0x1]	1284965	1			T75	280		T76	479		T77	76

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2480498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1274018

1

T75

225

T76

503

T77

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59445	1			T75	8		T76	43		T77	6
valid_sources[0x01]	59040	1			T75	8		T76	22		T77	3
valid_sources[0x02]	58916	1			T75	10		T76	29		T80	4
valid_sources[0x03]	58835	1			T75	8		T76	9		T156	93
valid_sources[0x04]	57256	1			T75	8		T76	15		T77	3
valid_sources[0x05]	58532	1			T75	10		T76	31		T77	5
valid_sources[0x06]	58226	1			T75	11		T76	48		T77	2
valid_sources[0x07]	59248	1			T75	12		T76	27		T77	6
valid_sources[0x08]	58941	1			T75	5		T76	20		T77	3
valid_sources[0x09]	58979	1			T75	12		T76	39		T77	4
valid_sources[0x0a]	59360	1			T75	12		T76	25		T77	3
valid_sources[0x0b]	59007	1			T75	7		T76	23		T77	5
valid_sources[0x0c]	58728	1			T75	7		T76	30		T77	5
valid_sources[0x0d]	57492	1			T75	9		T76	19		T77	3
valid_sources[0x0e]	58690	1			T75	12		T76	13		T77	3
valid_sources[0x0f]	59568	1			T75	13		T76	13		T77	2
valid_sources[0x10]	58046	1			T75	12		T76	13		T77	3
valid_sources[0x11]	59073	1			T75	12		T76	27		T77	5
valid_sources[0x12]	58266	1			T75	10		T76	12		T77	4
valid_sources[0x13]	57887	1			T75	12		T76	28		T77	6
valid_sources[0x14]	58380	1			T75	6		T76	22		T77	4
valid_sources[0x15]	58523	1			T75	6		T76	26		T77	1
valid_sources[0x16]	58219	1			T75	12		T76	36		T77	2
valid_sources[0x17]	59110	1			T75	10		T76	32		T77	5
valid_sources[0x18]	58707	1			T75	8		T76	10		T77	3
valid_sources[0x19]	59919	1			T75	9		T76	15		T77	4
valid_sources[0x1a]	58018	1			T75	14		T76	21		T77	3
valid_sources[0x1b]	58874	1			T75	6		T76	23		T77	1
valid_sources[0x1c]	58997	1			T75	11		T76	28		T77	4
valid_sources[0x1d]	58795	1			T75	8		T76	24		T77	5
valid_sources[0x1e]	58563	1			T75	7		T76	26		T77	3
valid_sources[0x1f]	58415	1			T75	15		T76	18		T77	2
valid_sources[0x20]	58014	1			T75	9		T76	23		T77	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

55678

1

T75

24

T76

12

T77

3

values[0x0]

all_enables

biggest_size

414174

1

T75

24

T76

175

T77

18

values[0x1]

all_enables

biggest_size

55147

1

T75

24

T76

23

T77

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3065482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

485202

1

T75

60

T76

219

T77

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1203283	1			T75	283		T76	500		T77	68
values[0x0]	1146165	1			T75	42		T76	493		T77	70
values[0x1]	1201236	1			T75	270		T76	531		T77	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2374086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1176598

1

T75

223

T76

492

T77

73

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56335	1			T75	7		T76	22		T77	1
valid_sources[0x01]	54950	1			T75	13		T76	27		T77	5
valid_sources[0x02]	55617	1			T75	8		T76	22		T77	7
valid_sources[0x03]	55110	1			T75	11		T76	20		T77	4
valid_sources[0x04]	54846	1			T75	6		T76	23		T77	6
valid_sources[0x05]	55542	1			T75	9		T76	23		T77	3
valid_sources[0x06]	54471	1			T75	7		T76	27		T77	4
valid_sources[0x07]	56210	1			T75	5		T76	24		T77	4
valid_sources[0x08]	54993	1			T75	9		T76	25		T77	4
valid_sources[0x09]	55052	1			T75	10		T76	26		T77	1
valid_sources[0x0a]	56340	1			T75	9		T76	22		T77	2
valid_sources[0x0b]	56448	1			T75	12		T76	22		T77	3
valid_sources[0x0c]	54659	1			T75	10		T76	27		T77	6
valid_sources[0x0d]	54940	1			T75	5		T76	19		T77	3
valid_sources[0x0e]	55287	1			T75	12		T76	23		T80	4
valid_sources[0x0f]	55221	1			T75	7		T76	19		T77	7
valid_sources[0x10]	55443	1			T75	12		T76	33		T77	7
valid_sources[0x11]	56081	1			T75	6		T76	26		T77	2
valid_sources[0x12]	55574	1			T75	6		T76	27		T77	6
valid_sources[0x13]	55508	1			T75	12		T76	23		T77	5
valid_sources[0x14]	55830	1			T75	5		T76	21		T77	5
valid_sources[0x15]	55098	1			T75	6		T76	28		T77	9
valid_sources[0x16]	55160	1			T75	10		T76	23		T77	2
valid_sources[0x17]	55478	1			T75	9		T76	26		T77	3
valid_sources[0x18]	55280	1			T75	18		T76	22		T77	4
valid_sources[0x19]	55153	1			T75	9		T76	26		T77	4
valid_sources[0x1a]	54601	1			T75	10		T76	34		T77	6
valid_sources[0x1b]	55498	1			T75	9		T76	24		T77	3
valid_sources[0x1c]	56359	1			T75	11		T76	18		T77	5
valid_sources[0x1d]	55323	1			T75	3		T76	17		T77	3
valid_sources[0x1e]	55668	1			T75	9		T76	18		T77	3
valid_sources[0x1f]	57124	1			T75	5		T76	24		T77	3
valid_sources[0x20]	56009	1			T75	11		T76	26		T77	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50854

1

T75

21

T76

27

T80

4

values[0x0]

all_enables

biggest_size

383593

1

T75

17

T76

173

T77

28

values[0x1]

all_enables

biggest_size

50755

1

T75

22

T76

19

T77

1