Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519166588	58188098	0	0
DepthKnown_A	519166588	519058290	0	0
RvalidKnown_A	519166588	519058290	0	0
WreadyKnown_A	519166588	519058290	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	58188098	0	0
T4	82177	9989	0	0
T5	243725	32133	0	0
T6	462407	58443	0	0
T17	286339	31211	0	0
T45	251180	32948	0	0
T55	149452	161922	0	0
T63	136922	18382	0	0
T66	271999	28367	0	0
T85	98846	13164	0	0
T86	375311	45756	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519166588	45624659	0	0
DepthKnown_A	519166588	519058290	0	0
RvalidKnown_A	519166588	519058290	0	0
WreadyKnown_A	519166588	519058290	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	45624659	0	0
T4	82177	7450	0	0
T5	243725	22483	0	0
T6	462407	53969	0	0
T17	286339	23791	0	0
T45	251180	23376	0	0
T55	149452	141944	0	0
T63	136922	13248	0	0
T66	271999	21451	0	0
T85	98846	9683	0	0
T86	375311	37703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519166588	43151754	0	0
DepthKnown_A	519166588	519058290	0	0
RvalidKnown_A	519166588	519058290	0	0
WreadyKnown_A	519166588	519058290	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	43151754	0	0
T4	82177	5671	0	0
T5	243725	15947	0	0
T6	462407	8436	0	0
T17	286339	17495	0	0
T45	251180	16604	0	0
T55	149452	201755	0	0
T63	136922	7529	0	0
T66	271999	14811	0	0
T85	98846	6773	0	0
T86	375311	21610	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519166588	36774763	0	0
DepthKnown_A	519166588	519058290	0	0
RvalidKnown_A	519166588	519058290	0	0
WreadyKnown_A	519166588	519058290	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	36774763	0	0
T4	82177	5539	0	0
T5	243725	15563	0	0
T6	462407	8159	0	0
T17	286339	17053	0	0
T45	251180	16221	0	0
T55	149452	147259	0	0
T63	136922	7251	0	0
T66	271999	14461	0	0
T85	98846	6591	0	0
T86	375311	21158	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519166588	519058290	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	91965	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	91965	0	0
T4	82177	15	0	0
T5	243725	151	0	0
T6	462407	30	0	0
T17	286339	64	0	0
T45	251180	151	0	0
T55	149452	41	0	0
T63	136922	26	0	0
T66	271999	103	0	0
T85	98846	19	0	0
T86	375311	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	94456	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	94456	0	0
T4	82177	15	0	0
T5	243725	151	0	0
T6	462407	30	0	0
T17	286339	64	0	0
T45	251180	151	0	0
T55	149452	41	0	0
T63	136922	26	0	0
T66	271999	103	0	0
T85	98846	19	0	0
T86	375311	60	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	52166	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	52166	0	0
T4	82177	14	0	0
T5	243725	95	0	0
T6	462407	28	0	0
T17	286339	59	0	0
T45	251180	95	0	0
T55	149452	12	0	0
T63	136922	23	0	0
T66	271999	95	0	0
T85	98846	18	0	0
T86	375311	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	52164	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	52164	0	0
T4	82177	14	0	0
T5	243725	95	0	0
T6	462407	28	0	0
T17	286339	59	0	0
T45	251180	95	0	0
T55	149452	12	0	0
T63	136922	23	0	0
T66	271999	95	0	0
T85	98846	18	0	0
T86	375311	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	39799	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	39799	0	0
T4	82177	1	0	0
T5	243725	56	0	0
T6	462407	2	0	0
T17	286339	5	0	0
T45	251180	56	0	0
T55	149452	29	0	0
T63	136922	3	0	0
T66	271999	8	0	0
T85	98846	1	0	0
T86	375311	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597474840	42292	0	0
DepthKnown_A	597474840	597354029	0	0
RvalidKnown_A	597474840	597354029	0	0
WreadyKnown_A	597474840	597354029	0	0
gen_passthru_fifo.paramCheckPass	2904	2904	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	42292	0	0
T4	82177	1	0	0
T5	243725	56	0	0
T6	462407	2	0	0
T17	286339	5	0	0
T45	251180	56	0	0
T55	149452	29	0	0
T63	136922	3	0	0
T66	271999	8	0	0
T85	98846	1	0	0
T86	375311	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597474840	597354029	0	0
T4	82177	82126	0	0
T5	243725	243619	0	0
T6	462407	462295	0	0
T17	286339	286190	0	0
T45	251180	251067	0	0
T55	149452	149446	0	0
T63	136922	136867	0	0
T66	271999	271882	0	0
T85	98846	98784	0	0
T86	375311	375150	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2904	2904	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0