Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T76,T156	Yes	T75,T76,T156	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T232,T233,T234	Yes	T232,T233,T234	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T232,T233,T234	Yes	T232,T233,T234	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T75,T77,T130	Yes	T75,T77,T130	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T5,T45,T208	Yes	T5,T45,T208	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T70,T67,T78	Yes	T70,T67,T78	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T70,*T67,*T71	Yes	T70,T67,T71	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T70,T67,T71	Yes	T70,T67,T71	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T8,T75,T76	Yes	T8,T75,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T77,T80	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T75,T80,T161	Yes	T75,T80,T161	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T75,T77	Yes	T8,T75,T80	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T8,T75,T80	Yes	T8,T75,T77	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T80,T160	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T8,T75,T161	Yes	T8,T75,T80	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T8,*T75,*T80	Yes	T8,T75,T77	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T268,*T269,*T270	Yes	T268,T269,T270	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T268,T269,T270	Yes	T268,T269,T270	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T268,*T269,*T270	Yes	T268,T269,T270	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T17	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T268,T8,T269	Yes	T268,T8,T269	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T8,T61	Yes	T60,T8,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T8,T61	Yes	T60,T8,T61	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T8,*T75,*T80	Yes	T8,T75,T80	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T413,T414,T415	Yes	T413,T414,T415	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T75,T80	Yes	T60,T8,T61	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T413,T414,T415	Yes	T60,T413,T414	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T8,T75,*T156	Yes	T8,T75,T80	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T412,*T413,*T8	Yes	T412,T413,T414	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T60,T412,T413	Yes	T60,T412,T413	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T5,T45,T208	Yes	T5,T45,T208	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T200,T211	Yes	T24,T200,T211	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T24,T162	Yes	T60,T223,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T75,T80,T131	Yes	T75,T80,T131	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T130,T131	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T223,*T24,*T162	Yes	T223,T24,T162	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T223,T162,T389	Yes	T223,T162,T389	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T162,T389	Yes	T60,T223,T162	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T223,T162,T389	Yes	T223,T162,T389	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T77,T80	Yes	T75,T80,T161	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T80,T130	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T223,*T162,*T389	Yes	T223,T162,T389	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T60,T223,T162	Yes	T60,T223,T162	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T149,*T75,*T80	Yes	T149,T75,T80	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T318,T223,T31	Yes	T318,T223,T31	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T318,T223,T31	Yes	T318,T223,T31	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T60,T318,T30	Yes	T318,T30,T223	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T80,T161	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T149,*T75,*T161	Yes	T149,T75,T80	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T60,*T318,*T30	Yes	T318,T30,T223	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T60,T318,T30	Yes	T60,T318,T30	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T161	Yes	T75,T80,T161	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T77,T80	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T80,T161	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T80,T130	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T75,T80,T161	Yes	T75,T80,T161	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T75,T80,T131	Yes	T75,T80,T161	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T130,T161	Yes	T75,T80,T130	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T75,T131,T161	Yes	T75,T80,T161	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T75,T161,T235	Yes	T75,T80,T131	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T75,*T161,*T235	Yes	T75,T131,T161	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T161	Yes	T75,T80,T161	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T116,T117,T676	Yes	T116,T117,T676	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T80,T161	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T75,*T161,*T235	Yes	T75,T80,T161	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T55,*T56,*T18	Yes	T55,T56,T18	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T60,T118,T162	Yes	T60,T118,T162	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T60,T118,T162	Yes	T60,T118,T162	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T118,T450,T451	Yes	T118,T450,T451	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	INPUT
tl_kmac_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T159,T185,T118	Yes	T159,T185,T118	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T185,T118	Yes	T159,T185,T118	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T159,T60,T185	Yes	T159,T185,T118	INPUT
tl_kmac_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T75,*T156,*T160	Yes	T75,T80,T156	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T159,*T60,*T185	Yes	T159,T185,T118	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T159,T60,T185	Yes	T159,T60,T185	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T131	Yes	T75,T80,T131	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T130,T131	Yes	T75,T130,T131	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T130,T131	Yes	T75,T80,T130	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T85,T128,T675	Yes	T85,T128,T675	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T128,T675	Yes	T85,T60,T128	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T85,T675,T271	Yes	T85,T60,T128	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T80,T131	Yes	T75,T80,T131	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T75,*T131,*T161	Yes	T75,T80,T131	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T130,T131	Yes	T75,T80,T130	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T85,*T128,*T675	Yes	T85,T128,T675	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T127,T128,T129	Yes	T127,T128,T129	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T80,T156	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T127,*T128,*T129	Yes	T55,T56,T127	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T4,T85,T60	Yes	T4,T85,T60	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T75,T76,T156	Yes	T75,T156,T130	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T4,T85,T128	Yes	T4,T85,T128	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T75,*T156,*T161	Yes	T75,T80,T156	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T4,*T85,*T128	Yes	T4,T85,T128	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T85,T60,T128	Yes	T85,T60,T128	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T85,T128,T129	Yes	T85,T128,T129	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T75,*T156,*T161	Yes	T75,T80,T156	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T85,*T128,*T129	Yes	T85,T128,T129	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T124	Yes	T128,T129,T124	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T128,T129,T124	Yes	T60,T128,T129	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T128,T129,T124	Yes	T60,T128,T129	INPUT
tl_edn1_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T76,T80	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T76,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T128,*T129,*T124	Yes	T128,T129,T124	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T60,T128,T129	Yes	T60,T128,T129	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T75,T76,T130	Yes	T75,T76,T130	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T80	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T75,T76,T131	Yes	T75,T76,T80	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T75,T76,T130	Yes	T75,T76,T130	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T45	Yes	T5,T17,T45	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T212	Yes	T78,T79,T212	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T76,T156	Yes	T75,T76,T80	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T195	Yes	T55,T56,T195	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T195	Yes	T55,T56,T195	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T55,T56,T60	Yes	T55,T56,T195	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T212	Yes	T78,T79,T212	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T75,T76,T156	Yes	T75,T76,T77	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T55,*T56,*T60	Yes	T55,T56,T195	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T55,T56,T60	Yes	T55,T56,T60	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T57,T159,T60	Yes	T57,T159,T60	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T75,*T80,*T161	Yes	T75,T80,T161	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_keymgr_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T130	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T57,T159,T185	Yes	T57,T159,T185	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T161,T235	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T75,*T156,*T161	Yes	T75,T76,T80	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T55,*T56,*T57	Yes	T55,T56,T57	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T8,*T75,*T80	Yes	T8,T75,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T8,T75,T80	Yes	T8,T75,T80	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T75,T131,T161	Yes	T75,T80,T131	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T8,*T75,*T76	Yes	T8,T75,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T76,T80	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T156	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T192,T306,T149	Yes	T192,T306,T149	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T190,T20	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T18,T190,T20	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T76,T131	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T190,*T191,*T120	Yes	T190,T441,T191	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range