Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T5,T45,T208	Yes	T5,T45,T208	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_uart0_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_uart0_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T149,*T75,*T80	Yes	T149,T75,T80	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T55,*T56,*T18	Yes	T55,T56,T18	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T227,T318,T121	Yes	T227,T318,T121	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T227,T318,T121	Yes	T227,T318,T121	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T227,T60,T318	Yes	T227,T60,T318	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T227,T60,T318	Yes	T227,T60,T318	INPUT
tl_uart1_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T227,T318,T121	Yes	T227,T318,T121	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T227,T318,T121	Yes	T227,T60,T318	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T227,T318,T121	Yes	T227,T60,T318	INPUT
tl_uart1_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T76,T80	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T149,*T75,*T161	Yes	T149,T75,T80	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T227,*T318,*T121	Yes	T227,T318,T121	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T227,T60,T318	Yes	T227,T60,T318	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T318,T331,T332	Yes	T318,T331,T332	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T318,T331,T332	Yes	T318,T331,T332	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T60,T318,T326	Yes	T60,T318,T326	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T60,T318,T326	Yes	T60,T318,T326	INPUT
tl_uart2_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T318,T331,T332	Yes	T318,T331,T332	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T318,T326,T331	Yes	T60,T318,T326	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T318,T326,T331	Yes	T60,T318,T326	INPUT
tl_uart2_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T149,*T75,*T80	Yes	T149,T75,T80	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T318,*T331,*T332	Yes	T318,T331,T332	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T60,T318,T326	Yes	T60,T318,T326	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T318,T27,T28	Yes	T318,T27,T28	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T318,T27,T28	Yes	T318,T27,T28	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T60,T318,T27	Yes	T60,T318,T27	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T60,T318,T27	Yes	T60,T318,T27	INPUT
tl_uart3_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T318,T27,T28	Yes	T318,T27,T28	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T318,T27,T326	Yes	T60,T318,T27	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T318,T27,T326	Yes	T60,T318,T27	INPUT
tl_uart3_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T149,*T75,*T156	Yes	T149,T75,T77	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T75,T156,T130	Yes	T75,T77,T80	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T318,*T27,*T28	Yes	T318,T27,T28	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T60,T318,T27	Yes	T60,T318,T27	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T223,T225,T389	Yes	T223,T225,T389	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T223,T225,T389	Yes	T223,T225,T389	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_i2c0_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T225,T226,T284	Yes	T225,T226,T284	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T326,T225	Yes	T60,T223,T326	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T223,T326,T225	Yes	T60,T223,T326	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T75,T80,T131	Yes	T75,T131,T161	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T75,*T131,*T161	Yes	T75,T80,T131	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T223,*T225,*T389	Yes	T223,T225,T389	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T223,T389,T324	Yes	T223,T389,T324	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T223,T389,T324	Yes	T223,T389,T324	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_i2c1_i.d_error	Yes	Yes	T75,T76,T156	Yes	T75,T76,T156	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T324,T284,T333	Yes	T324,T284,T333	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T326,T389	Yes	T60,T223,T326	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T223,T326,T389	Yes	T60,T223,T326	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T156	Yes	T75,T76,T80	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T223,*T389,*T324	Yes	T223,T389,T324	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T223,T334,T389	Yes	T223,T334,T389	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T223,T334,T389	Yes	T223,T334,T389	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_i2c2_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T80,T130	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T334,T340,T284	Yes	T334,T340,T284	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T326,T334	Yes	T60,T223,T326	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T223,T326,T334	Yes	T60,T223,T326	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T75,T161,T235	Yes	T75,T160,T161	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T75,*T161,*T235	Yes	T75,T76,T80	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T75,T156,T130	Yes	T75,T80,T130	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T223,*T334,*T389	Yes	T223,T334,T389	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T60,T223,T326	Yes	T60,T223,T326	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T162,T229,T230	Yes	T162,T229,T230	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T162,T229,T230	Yes	T162,T229,T230	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T60,T162,T229	Yes	T60,T162,T229	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T60,T162,T229	Yes	T60,T162,T229	INPUT
tl_pattgen_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T162,T229,T230	Yes	T162,T229,T230	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T162,T229,T230	Yes	T60,T162,T229	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T162,T229,T230	Yes	T60,T162,T229	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T80,T161	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T75,*T156,*T161	Yes	T75,T80,T161	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T130,T161	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T162,*T229,*T230	Yes	T162,T229,T230	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T60,T162,T229	Yes	T60,T162,T229	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T110,T186	Yes	T6,T110,T186	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T6,T110,T186	Yes	T6,T110,T186	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T6,T110,T60	Yes	T6,T110,T60	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T6,T110,T60	Yes	T6,T110,T60	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T75,T156,T130	Yes	T75,T156,T130	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T110,T186	Yes	T6,T110,T186	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T110,T186	Yes	T6,T110,T60	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T6,T110,T186	Yes	T6,T110,T60	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T75,T156,T160	Yes	T75,T156,T160	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T8,T75,*T156	Yes	T8,T75,T80	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T75,T156,T130	Yes	T75,T156,T130	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T6,*T110,*T186	Yes	T6,T110,T186	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T6,T110,T60	Yes	T6,T110,T60	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T130,T161	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T29,T284,T38	Yes	T29,T284,T38	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T29,T284	Yes	T110,T60,T153	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T110,T29,T284	Yes	T110,T60,T153	INPUT
tl_gpio_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T161,T235	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T75,*T161,*T235	Yes	T75,T161,T235	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T130,T131	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	INPUT
tl_spi_device_i.d_error	Yes	Yes	T75,T130,T131	Yes	T75,T76,T130	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T223,T24,T162	Yes	T223,T24,T162	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T60,T223,T24	Yes	T223,T24,T162	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T75,T80,T131	Yes	T75,T156,T131	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T80,T130	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T60,*T223,*T24	Yes	T223,T24,T162	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T60,T223,T24	Yes	T60,T223,T24	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T110,T265,T153	Yes	T110,T265,T153	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T110,T265,T153	Yes	T110,T265,T153	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T110,T60,T265	Yes	T110,T60,T265	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T110,T60,T265	Yes	T110,T60,T265	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T265,T162,T103	Yes	T265,T162,T103	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T265,T153	Yes	T110,T60,T265	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T110,T265,T153	Yes	T110,T60,T265	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T75,T80,T161	Yes	T75,T161,T235	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T77,T130	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T110,*T265,*T153	Yes	T110,T265,T153	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T110,T60,T265	Yes	T110,T60,T265	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T156,T130	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T75,T156,T161	Yes	T75,T156,T161	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T75,*T156	Yes	T8,T75,T80	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T55	Yes	T6,T17,T55	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T6,T17,T55	Yes	T6,T17,T55	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T75,T156,T130	Yes	T75,T156,T130	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T156,T161	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T8,*T75,*T156	Yes	T8,T75,T80	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T59,T227,T57	Yes	T59,T227,T57	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T59,T227,T57	Yes	T59,T227,T57	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T75,T130,T131	Yes	T75,T130,T131	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T59,T227,T27	Yes	T59,T227,T27	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T17,T45	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T131,T161	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T131	Yes	T158,T448,T679	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T130,T131	Yes	T75,T130,T131	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T59,*T227,*T57	Yes	T59,T227,T57	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T80	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T8,*T75,*T76	Yes	T8,T75,T76	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T80	Yes	T75,T76,T77	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T75,T77,T156	Yes	T75,T156,T130	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T77,T80	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T71,*T157,*T158	Yes	T71,T157,T158	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T80,T156	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T66,*T110,*T159	Yes	T66,T110,T159	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T75,T160,T161	Yes	T75,T80,T156	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T76,T80	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T75,T80,T160	Yes	T75,T80,T160	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T17	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T75,T77,T156	Yes	T75,T156,T130	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T65,T179	Yes	T60,T64,T65	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T75,T77,T156	Yes	T75,T156,T131	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T268,*T270,*T313	Yes	T268,T270,T313	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T75,T77,T156	Yes	T75,T156,T130	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T18,*T159,*T185	Yes	T55,T56,T18	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T80,T130	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T56,T18,T20	Yes	T56,T18,T20	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T56,T18,T20	Yes	T56,T18,T60	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T17,T45	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T161,T235	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T156,T130	Yes	T75,T130,T131	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T45	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T75,T77,T130	Yes	T75,T130,T131	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T75,T77,T161	Yes	T75,T161,T235	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T75,*T77,*T161	Yes	T75,T161,T235	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T45,*T66	Yes	T5,T45,T55	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T45,T55	Yes	T5,T45,T55	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T75,T77,T130	Yes	T75,T77,T130	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T190,T191,T120	Yes	T190,T191,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T190,T20	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T18,T190,T20	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T75,T77,T80	Yes	T75,T77,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T75,T77,T80	Yes	T75,T77,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T190,*T191,*T120	Yes	T190,T441,T191	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T55,T56,T18	Yes	T55,T56,T18	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T17,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T80,T160	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T212	Yes	T78,T79,T212	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T75,T80,T160	Yes	T75,T76,T80	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T156	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T45	Yes	T5,T17,T45	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T160	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T75,*T156,*T161	Yes	T269,T680,T75	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T86,T199,T318	Yes	T86,T199,T318	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T86,T199,T318	Yes	T86,T199,T318	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T86,T199,T60	Yes	T86,T199,T60	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T86,T199,T60	Yes	T86,T199,T60	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T86,T199,T318	Yes	T86,T199,T318	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T199,T318	Yes	T86,T199,T60	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T86,T199,T267	Yes	T86,T199,T60	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T75,T161,T235	Yes	T75,T80,T161	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T149,*T213,*T75	Yes	T149,T213,T75	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T130,T161	Yes	T75,T130,T161	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T86,*T199,*T318	Yes	T86,T199,T318	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T86,T199,T60	Yes	T86,T199,T60	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T110,T111,T1	Yes	T110,T111,T1	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T110,T111,T1	Yes	T110,T111,T1	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T110,T60,T111	Yes	T110,T60,T111	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T110,T60,T111	Yes	T110,T60,T111	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T111,T1,T2	Yes	T111,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T111,T1	Yes	T110,T60,T111	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T110,T111,T1	Yes	T110,T60,T111	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T156	Yes	T75,T80,T156	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T80,T156	Yes	T75,T80,T156	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T110,*T111,*T1	Yes	T110,T111,T1	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T110,T60,T111	Yes	T110,T60,T111	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T79	Yes	T71,T78,T79	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T78,T79,T8	Yes	T78,T79,T8	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T75,T80,T131	Yes	T75,T80,T131	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T75,T80,T131	Yes	T75,T80,T131	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T131	Yes	T75,T80,T131	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T75,T80,T130	Yes	T75,T80,T130	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T75,*T80,*T130	Yes	T75,T80,T130	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range