Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.50	95.29	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	1033476586	4373	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	1033476586	4373	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	4373	0	0
T4	278828	4	0	0
T5	862854	14	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T35	987089	0	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0
T160	181409	0	0	0
T195	100189	8	0	0
T196	92365	9	0	0
T197	0	11	0	0
T312	0	8	0	0
T313	0	8	0	0
T314	0	9	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	4373	0	0
T4	278828	4	0	0
T5	862854	14	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T35	987089	0	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0
T160	181409	0	0	0
T195	100189	8	0	0
T196	92365	9	0	0
T197	0	11	0	0
T312	0	8	0	0
T313	0	8	0	0
T314	0	9	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	516738293	53	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	516738293	53	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	53	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	8	0	0
T196	92365	9	0	0
T197	0	11	0	0
T312	0	8	0	0
T313	0	8	0	0
T314	0	9	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	53	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	8	0	0
T196	92365	9	0	0
T197	0	11	0	0
T312	0	8	0	0
T313	0	8	0	0
T314	0	9	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	516738293	4320	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	516738293	4320	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	4320	0	0
T4	278828	4	0	0
T5	862854	14	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	4320	0	0
T4	278828	4	0	0
T5	862854	14	0	0
T6	204222	1	0	0
T15	213648	1	0	0
T16	152738	1	0	0
T44	199003	2	0	0
T45	217490	2	0	0
T92	69384	1	0	0
T93	90956	1	0	0
T94	89313	1	0	0