Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_core_ibex
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.26 95.29 89.29 98.53 100.00 68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex 90.50 95.29 89.29 99.75 100.00 68.18



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.50 95.29 89.29 99.75 100.00 68.18


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.44 97.51 95.86 98.06 98.66 92.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.62 88.53 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
fifo_d 100.00 100.00 100.00 100.00 100.00
fifo_i 93.75 75.00 100.00 100.00 100.00
gen_alert_senders[0].u_alert_sender 75.00 75.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 75.00 75.00
tl_adapter_host_d_ibex 91.79 95.35 81.82 90.00 100.00
tl_adapter_host_i_ibex 87.90 90.48 72.22 88.89 100.00
u_alert_nmi_sync 100.00 100.00 100.00
u_core 95.91 95.91
u_core_sleeping_buf 100.00 100.00
u_dbus_trans 96.36 100.00 92.59 100.00 92.86
u_edn_if 89.08 100.00 86.44 94.87 75.00
u_ibus_trans 96.36 100.00 92.59 100.00 92.86
u_intr_timer_sync 100.00 100.00 100.00
u_lc_sync 100.00 100.00 100.00 100.00
u_prim_buf_irq 100.00 100.00
u_prim_esc_receiver 100.00 100.00
u_prim_lc_sender 100.00 100.00 100.00
u_prim_sync_reqack_data 91.67 100.00 66.67 100.00 100.00
u_pwrmgr_sync 100.00 100.00 100.00 100.00
u_reg_cfg 99.24 98.69 98.69 99.58 100.00
u_sim_win_rsp 89.32 77.27 80.00 100.00 100.00
u_tlul_req_buf 100.00 100.00
u_tlul_rsp_buf 100.00 100.00
u_wdog_nmi_sync 100.00 100.00 100.00

Line Coverage for Module : rv_core_ibex
Line No.TotalCoveredPercent
TOTAL858195.29
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN36311100.00
ALWAYS49233100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51511100.00
ALWAYS51888100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN71911100.00
CONT_ASSIGN72211100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN72611100.00
CONT_ASSIGN72811100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN751100.00
CONT_ASSIGN75211100.00
CONT_ASSIGN75311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN75711100.00
CONT_ASSIGN76011100.00
ALWAYS7921111100.00
ALWAYS80877100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN83811100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84011100.00
CONT_ASSIGN843100.00
CONT_ASSIGN84700
CONT_ASSIGN88611100.00
ALWAYS94500
CONT_ASSIGN986100.00
CONT_ASSIGN988100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
202 1 1
203 1 1
216 1 1
217 1 1
218 1 1
225 1 1
263 1 1
265 1 1
268 1 1
342 1 1
348 1 1
363 1 1
492 1 1
493 1 1
495 1 1
512 1 1
513 1 1
514 1 1
515 1 1
518 1 1
519 1 1
520 1 1
521 1 1
522 1 1
523 1 1
524 1 1
525 1 1
MISSING_ELSE
702 2 2
703 2 2
704 2 2
708 2 2
709 2 2
710 2 2
717 1 1
718 1 1
719 1 1
722 1 1
724 1 1
726 1 1
728 1 1
735 1 1
737 1 1
739 1 1
741 1 1
751 0 1
752 1 1
753 1 1
754 1 1
757 1 1
760 1 1
792 1 1
793 1 1
794 1 1
796 1 1
797 1 1
798 1 1
799 1 1
800 1 1
801 1 1
802 1 1
803 1 1
MISSING_ELSE
808 1 1
809 1 1
810 1 1
811 1 1
813 1 1
814 1 1
815 1 1
819 1 1
838 1 1
839 1 1
840 1 1
843 0 1
847 unreachable
886 1 1
945 unreachable
946 unreachable
947 unreachable
948 unreachable
==> MISSING_ELSE
986 0 1
988 0 1
990 1 1
992 1 1
994 1 1


Cond Coverage for Module : rv_core_ibex
TotalCoveredPercent
Conditions282589.29
Logical282589.29
Non-Logical00
Event00

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT255,T125,T193
010Not Covered
100Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT256,T257,T258
10CoveredT45,T17,T18

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT45,T17,T18

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T6,T44
11CoveredT61,T62,T8

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT61,T62,T8
10CoveredT4,T5,T6
11CoveredT73,T61,T62

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T5,T6
11CoveredT61,T62,T8

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T6,T44
11CoveredT61,T62,T8

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT45,T17,T18
010CoveredT255,T125,T193
100CoveredT259,T260

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T44
11CoveredT4,T5,T6

Toggle Coverage for Module : rv_core_ibex
TotalCoveredPercent
Totals 123 117 95.12
Total Bits 1628 1604 98.53
Total Bits 0->1 814 802 98.53
Total Bits 1->0 814 802 98.53

Ports 123 117 95.12
Port Bits 1628 1604 98.53
Port Bits 0->1 814 802 98.53
Port Bits 1->0 814 802 98.53

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
clk_edn_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_edn_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
rst_cpu_n_o Yes Yes T4,T5,T44 Yes T4,T5,T6 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_o.d_ready Yes Yes T84,T85,T87 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_user.data_intg[6:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_o.a_user.instr_type[3:0] Yes Yes T84,T135,T261 Yes T84,T135,T261 OUTPUT
corei_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_data[31:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_mask[3:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_address[31:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_opcode[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_error Yes Yes T177,T108,T113 Yes T177,T108,T113 INPUT
corei_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T177,T108,T113 Yes T177,T108,T113 INPUT
corei_tl_h_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
corei_tl_h_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
corei_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_o.d_ready Yes Yes T58,T76,T86 Yes T58,T76,T86 OUTPUT
cored_tl_h_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_user.instr_type[3:0] Yes Yes T58,T8,T84 Yes T58,T8,T84 OUTPUT
cored_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_address[31:0] Yes Yes T58,T8,T83 Yes T58,T8,T83 OUTPUT
cored_tl_h_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_size[1:0] Yes Yes T58,T8,T83 Yes T58,T8,T83 OUTPUT
cored_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_error Yes Yes T4,T68,T69 Yes T4,T68,T69 INPUT
cored_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cored_tl_h_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cored_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
irq_software_i Yes Yes T262,T263,T264 Yes T262,T263,T264 INPUT
irq_timer_i Yes Yes T265,T168,T266 Yes T265,T168,T266 INPUT
irq_external_i Yes Yes T4,T15,T16 Yes T4,T15,T16 INPUT
esc_tx_i.esc_n Yes Yes T4,T123,T65 Yes T4,T123,T65 INPUT
esc_tx_i.esc_p Yes Yes T4,T123,T65 Yes T4,T123,T65 INPUT
esc_rx_o.resp_n Yes Yes T4,T123,T65 Yes T4,T123,T65 OUTPUT
esc_rx_o.resp_p Yes Yes T4,T123,T65 Yes T4,T123,T65 OUTPUT
nmi_wdog_i Yes Yes T186,T68,T109 Yes T186,T68,T109 INPUT
debug_req_i Yes Yes T74,T267,T268 Yes T74,T267,T268 INPUT
crash_dump_o.current.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_valid Unreachable Unreachable Unreachable OUTPUT
lc_cpu_en_i[3:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
pwrmgr_cpu_en_i[3:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
pwrmgr_o.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_data[31:0] Yes Yes T4,T6,T44 Yes T4,T6,T44 INPUT
cfg_tl_d_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[7:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[20:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_source[5:0] Yes Yes *T8,*T9,*T269 Yes T8,T9,T269 INPUT
cfg_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_opcode[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_error Yes Yes T8,T9,T83 Yes T8,T9,T83 OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0] Yes Yes T4,T5,T65 Yes T4,T5,T65 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_data[31:0] Yes Yes T4,T5,T65 Yes T4,T5,T65 OUTPUT
cfg_tl_d_o.d_sink Yes Yes T83,T84,T85 Yes T84,T85,T87 OUTPUT
cfg_tl_d_o.d_source[5:0] Yes Yes *T8,*T9,*T84 Yes T8,T9,T269 OUTPUT
cfg_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_size[1:0] Yes Yes T84,T85,T134 Yes T83,T84,T85 OUTPUT
cfg_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T5,T45 Yes T4,T5,T92 INPUT
edn_i.edn_fips Yes Yes T270,T271,T272 Yes T123,T270,T273 INPUT
edn_i.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_o.req Yes Yes T113,T194,T195 Yes T113,T194,T195 OUTPUT
icache_otp_key_i.seed_valid Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_i.nonce[127:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_i.key[127:0] Yes Yes T4,T5,T44 Yes T4,T5,T44 INPUT
icache_otp_key_i.ack Yes Yes T195,T196,T197 Yes T195,T196,T197 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i[0].ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[0].ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T73,T61,T62 Yes T73,T61,T62 INPUT
alert_rx_i[1].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[1].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[2].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[2].ack_p Yes Yes T259,T255,T125 Yes T259,T255,T125 INPUT
alert_rx_i[2].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[2].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[3].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[3].ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i[3].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[3].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T73,T61,T62 Yes T73,T61,T62 OUTPUT
alert_tx_o[2].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[2].alert_p Yes Yes T259,T255,T125 Yes T259,T274,T255 OUTPUT
alert_tx_o[3].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[3].alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_core_ibex
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 348 2 2 100.00
IF 492 2 2 100.00
IF 518 3 3 100.00
IF 796 3 3 100.00
IF 808 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 348 (fatal_core_err) ?

Branches:
-1-StatusTests
1 Covered T45,T17,T18
0 Covered T4,T5,T6


LineNo. Expression -1-: 492 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 518 if ((!rst_ni)) -2-: 522 if (double_fault)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T256,T257,T258
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 796 if (reg2hw.rnd_data.re) -2-: 800 if ((edn_req && edn_ack))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T123
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 808 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : rv_core_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 15 68.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 15 68.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmIbexFetchEnable0_A 516738293 4 0 0
FpvSecCmIbexFetchEnable1_A 516738293 24966415 0 90
FpvSecCmIbexFetchEnable2_A 516738293 66251213 0 78
FpvSecCmIbexFetchEnable3Rev_A 516738293 445963857 0 2006
FpvSecCmIbexFetchEnable3_A 516738293 445965735 0 1904
FpvSecCmIbexInstrIntgErrCheck_A 516738293 77 0 0
FpvSecCmIbexLoadRespIntgErrCheck_A 516738293 589 0 0
FpvSecCmIbexLockstepResetCountAlertCheck_A 516738293 0 0 0
FpvSecCmIbexPcMismatchCheck_A 516738293 0 0 0
FpvSecCmIbexRfEccErrCheck_A 516738293 0 0 0
FpvSecCmIbexStoreRespIntgErrCheck_A 516738293 0 0 0
FpvSecCmRegWeOnehotCheck_A 516738293 2 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 516738293 0 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 516738293 0 0 0
FpvSecCmRvCoreRegWeOnehotCheck_A 516738293 0 0 0
g_instr_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 1017 1017 0 0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A 1017 1017 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 516738293 217 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 516738293 203 0 0


FpvSecCmIbexFetchEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 4 0 0
T107 155983 0 0 0
T256 225021 1 0 0
T257 0 1 0 0
T258 0 1 0 0
T275 0 1 0 0
T276 224936 0 0 0
T277 228529 0 0 0
T278 139768 0 0 0
T279 195890 0 0 0
T280 377536 0 0 0
T281 190818 0 0 0
T282 292046 0 0 0
T283 123371 0 0 0

FpvSecCmIbexFetchEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 24966415 0 90
T4 278828 41066 0 0
T5 862854 10008 0 2
T6 204222 9923 0 0
T15 213648 9919 0 0
T16 152738 9931 0 0
T18 0 0 0 2
T44 199003 29831 0 0
T45 217490 19854 0 0
T57 0 0 0 2
T58 0 0 0 2
T67 0 0 0 2
T76 0 0 0 2
T86 0 0 0 2
T92 69384 9931 0 0
T93 90956 9923 0 0
T94 89313 9927 0 0
T188 0 0 0 2
T284 0 0 0 2
T285 0 0 0 2

FpvSecCmIbexFetchEnable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 66251213 0 78
T4 278828 69555 0 0
T5 862854 34852 0 2
T6 204222 34775 0 0
T15 213648 34775 0 0
T16 152738 34775 0 0
T18 0 0 0 2
T19 0 0 0 2
T44 199003 104332 0 0
T45 217490 69555 0 0
T57 0 0 0 2
T58 0 0 0 2
T76 0 0 0 2
T86 0 0 0 2
T92 69384 34775 0 0
T93 90956 34775 0 0
T94 89313 34775 0 0
T188 0 0 0 2
T246 0 0 0 2
T285 0 0 0 2

FpvSecCmIbexFetchEnable3Rev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 445963857 0 2006
T4 278828 187939 0 2
T5 862854 827884 0 2
T6 204222 169393 0 2
T15 213648 178819 0 2
T16 152738 117902 0 2
T44 199003 94547 0 2
T45 217490 147817 0 2
T92 69384 34548 0 2
T93 90956 56123 0 2
T94 89313 54473 0 2

FpvSecCmIbexFetchEnable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 445965735 0 1904
T4 278828 187941 0 2
T5 862854 827885 0 0
T6 204222 169394 0 2
T15 213648 178820 0 2
T16 152738 117903 0 2
T44 199003 94549 0 2
T45 217490 147818 0 2
T60 0 0 0 2
T92 69384 34549 0 2
T93 90956 56124 0 2
T94 89313 54474 0 2

FpvSecCmIbexInstrIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 77 0 0
T116 194414 0 0 0
T189 50214 0 0 0
T286 266855 77 0 0
T287 130715 0 0 0
T288 213494 0 0 0
T289 202198 0 0 0
T290 242051 0 0 0
T291 158619 0 0 0
T292 201989 0 0 0
T293 161250 0 0 0

FpvSecCmIbexLoadRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 589 0 0
T125 201546 32 0 0
T193 0 32 0 0
T225 158194 0 0 0
T255 258493 1 0 0
T265 79883 0 0 0
T294 0 32 0 0
T295 0 1 0 0
T296 0 100 0 0
T297 0 1 0 0
T298 0 1 0 0
T299 0 99 0 0
T300 0 32 0 0
T301 106720 0 0 0
T302 94215 0 0 0
T303 97738 0 0 0
T304 184272 0 0 0
T305 368700 0 0 0
T306 236175 0 0 0

FpvSecCmIbexLockstepResetCountAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexPcMismatchCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexRfEccErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexStoreRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 2 0 0
T76 113290 0 0 0
T173 143288 0 0 0
T259 262146 1 0 0
T260 0 1 0 0
T267 196763 0 0 0
T274 54258 0 0 0
T307 134811 0 0 0
T308 260354 0 0 0
T309 160690 0 0 0
T310 93013 0 0 0
T311 517602 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRvCoreRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

g_instr_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 217 0 0
T35 987089 0 0 0
T160 181409 0 0 0
T195 100189 33 0 0
T196 92365 36 0 0
T197 0 45 0 0
T312 0 33 0 0
T313 0 33 0 0
T314 0 37 0 0
T315 648058 0 0 0
T316 118042 0 0 0
T317 117075 0 0 0
T318 303251 0 0 0
T319 272002 0 0 0
T320 143633 0 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 203 0 0
T26 606397 0 0 0
T55 118084 0 0 0
T113 268343 16 0 0
T114 92157 0 0 0
T124 63262 0 0 0
T172 246327 0 0 0
T194 0 16 0 0
T195 0 42 0 0
T196 0 9 0 0
T197 0 11 0 0
T312 0 42 0 0
T313 0 42 0 0
T314 0 9 0 0
T321 0 16 0 0
T322 198328 0 0 0
T323 204196 0 0 0
T324 133594 0 0 0
T325 281060 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
Line No.TotalCoveredPercent
TOTAL858195.29
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN34211100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN36311100.00
ALWAYS49233100.00
CONT_ASSIGN51211100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51411100.00
CONT_ASSIGN51511100.00
ALWAYS51888100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN70911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN71811100.00
CONT_ASSIGN71911100.00
CONT_ASSIGN72211100.00
CONT_ASSIGN72411100.00
CONT_ASSIGN72611100.00
CONT_ASSIGN72811100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN751100.00
CONT_ASSIGN75211100.00
CONT_ASSIGN75311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN75711100.00
CONT_ASSIGN76011100.00
ALWAYS7921111100.00
ALWAYS80877100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN83811100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84011100.00
CONT_ASSIGN843100.00
CONT_ASSIGN84700
CONT_ASSIGN88611100.00
ALWAYS94500
CONT_ASSIGN986100.00
CONT_ASSIGN988100.00
CONT_ASSIGN99011100.00
CONT_ASSIGN99211100.00
CONT_ASSIGN99411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
202 1 1
203 1 1
216 1 1
217 1 1
218 1 1
225 1 1
263 1 1
265 1 1
268 1 1
342 1 1
348 1 1
363 1 1
492 1 1
493 1 1
495 1 1
512 1 1
513 1 1
514 1 1
515 1 1
518 1 1
519 1 1
520 1 1
521 1 1
522 1 1
523 1 1
524 1 1
525 1 1
MISSING_ELSE
702 2 2
703 2 2
704 2 2
708 2 2
709 2 2
710 2 2
717 1 1
718 1 1
719 1 1
722 1 1
724 1 1
726 1 1
728 1 1
735 1 1
737 1 1
739 1 1
741 1 1
751 0 1
752 1 1
753 1 1
754 1 1
757 1 1
760 1 1
792 1 1
793 1 1
794 1 1
796 1 1
797 1 1
798 1 1
799 1 1
800 1 1
801 1 1
802 1 1
803 1 1
MISSING_ELSE
808 1 1
809 1 1
810 1 1
811 1 1
813 1 1
814 1 1
815 1 1
819 1 1
838 1 1
839 1 1
840 1 1
843 0 1
847 unreachable
886 1 1
945 unreachable
946 unreachable
947 unreachable
948 unreachable
==> MISSING_ELSE
986 0 1
988 0 1
990 1 1
992 1 1
994 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalCoveredPercent
Conditions282589.29
Logical282589.29
Non-Logical00
Event00

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT255,T125,T193
010Not Covered
100Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT256,T257,T258
10CoveredT45,T17,T18

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT45,T17,T18

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T6,T44
11CoveredT61,T62,T8

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT61,T62,T8
10CoveredT4,T5,T6
11CoveredT73,T61,T62

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T5,T6
11CoveredT61,T62,T8

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------
-1--2-StatusTests
01CoveredT73,T61,T62
10CoveredT4,T6,T44
11CoveredT61,T62,T8

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT45,T17,T18
010CoveredT255,T125,T193
100CoveredT259,T260

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T44
11CoveredT4,T5,T6

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalCoveredPercent
Totals 119 117 98.32
Total Bits 1608 1604 99.75
Total Bits 0->1 804 802 99.75
Total Bits 1->0 804 802 99.75

Ports 119 117 98.32
Port Bits 1608 1604 99.75
Port Bits 0->1 804 802 99.75
Port Bits 1->0 804 802 99.75

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
clk_edn_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_edn_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
rst_cpu_n_o Yes Yes T4,T5,T44 Yes T4,T5,T6 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test No No No INPUT
hart_id_i[31:0] Unreachable Unreachable Unreachable INPUT
boot_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_o.d_ready Yes Yes T84,T85,T87 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_user.data_intg[6:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_o.a_user.instr_type[3:0] Yes Yes T84,T135,T261 Yes T84,T135,T261 OUTPUT
corei_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_data[31:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_mask[3:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_address[31:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
corei_tl_h_o.a_opcode[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
corei_tl_h_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
corei_tl_h_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_error Yes Yes T177,T108,T113 Yes T177,T108,T113 INPUT
corei_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T177,T108,T113 Yes T177,T108,T113 INPUT
corei_tl_h_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
corei_tl_h_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
corei_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
corei_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
corei_tl_h_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_o.d_ready Yes Yes T58,T76,T86 Yes T58,T76,T86 OUTPUT
cored_tl_h_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_user.instr_type[3:0] Yes Yes T58,T8,T84 Yes T58,T8,T84 OUTPUT
cored_tl_h_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_address[31:0] Yes Yes T58,T8,T83 Yes T58,T8,T83 OUTPUT
cored_tl_h_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_size[1:0] Yes Yes T58,T8,T83 Yes T58,T8,T83 OUTPUT
cored_tl_h_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cored_tl_h_o.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cored_tl_h_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_error Yes Yes T4,T68,T69 Yes T4,T68,T69 INPUT
cored_tl_h_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_sink Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cored_tl_h_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cored_tl_h_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cored_tl_h_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
cored_tl_h_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
irq_software_i Yes Yes T262,T263,T264 Yes T262,T263,T264 INPUT
irq_timer_i Yes Yes T265,T168,T266 Yes T265,T168,T266 INPUT
irq_external_i Yes Yes T4,T15,T16 Yes T4,T15,T16 INPUT
esc_tx_i.esc_n Yes Yes T4,T123,T65 Yes T4,T123,T65 INPUT
esc_tx_i.esc_p Yes Yes T4,T123,T65 Yes T4,T123,T65 INPUT
esc_rx_o.resp_n Yes Yes T4,T123,T65 Yes T4,T123,T65 OUTPUT
esc_rx_o.resp_p Yes Yes T4,T123,T65 Yes T4,T123,T65 OUTPUT
nmi_wdog_i Yes Yes T186,T68,T109 Yes T186,T68,T109 INPUT
debug_req_i Yes Yes T74,T267,T268 Yes T74,T267,T268 INPUT
crash_dump_o.current.exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.last_data_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.next_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.current.current_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_addr[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_exception_pc[31:0] Unreachable Unreachable Unreachable OUTPUT
crash_dump_o.prev_valid Unreachable Unreachable Unreachable OUTPUT
lc_cpu_en_i[3:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
pwrmgr_cpu_en_i[3:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
pwrmgr_o.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_data[31:0] Yes Yes T4,T6,T44 Yes T4,T6,T44 INPUT
cfg_tl_d_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[7:0] Yes Yes *T83,*T84,*T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[20:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
cfg_tl_d_i.a_address[31] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_source[5:0] Yes Yes *T8,*T9,*T269 Yes T8,T9,T269 INPUT
cfg_tl_d_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_size[1:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
cfg_tl_d_i.a_opcode[2:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 INPUT
cfg_tl_d_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cfg_tl_d_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_error Yes Yes T8,T9,T83 Yes T8,T9,T83 OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0] Yes Yes T4,T5,T65 Yes T4,T5,T65 OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_data[31:0] Yes Yes T4,T5,T65 Yes T4,T5,T65 OUTPUT
cfg_tl_d_o.d_sink Yes Yes T83,T84,T85 Yes T84,T85,T87 OUTPUT
cfg_tl_d_o.d_source[5:0] Yes Yes *T8,*T9,*T84 Yes T8,T9,T269 OUTPUT
cfg_tl_d_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_size[1:0] Yes Yes T84,T85,T134 Yes T83,T84,T85 OUTPUT
cfg_tl_d_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
cfg_tl_d_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
cfg_tl_d_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i.edn_bus[31:0] Yes Yes T4,T5,T45 Yes T4,T5,T92 INPUT
edn_i.edn_fips Yes Yes T270,T271,T272 Yes T123,T270,T273 INPUT
edn_i.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_o.req Yes Yes T113,T194,T195 Yes T113,T194,T195 OUTPUT
icache_otp_key_i.seed_valid Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_i.nonce[127:0] Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
icache_otp_key_i.key[127:0] Yes Yes T4,T5,T44 Yes T4,T5,T44 INPUT
icache_otp_key_i.ack Yes Yes T195,T196,T197 Yes T195,T196,T197 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i[0].ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[0].ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T73,T61,T62 Yes T73,T61,T62 INPUT
alert_rx_i[1].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[1].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[2].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[2].ack_p Yes Yes T259,T255,T125 Yes T259,T255,T125 INPUT
alert_rx_i[2].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[2].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[3].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[3].ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i[3].ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i[3].ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T73,T61,T62 Yes T73,T61,T62 OUTPUT
alert_tx_o[2].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[2].alert_p Yes Yes T259,T255,T125 Yes T259,T274,T255 OUTPUT
alert_tx_o[3].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[3].alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 348 2 2 100.00
IF 492 2 2 100.00
IF 518 3 3 100.00
IF 796 3 3 100.00
IF 808 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 348 (fatal_core_err) ?

Branches:
-1-StatusTests
1 Covered T45,T17,T18
0 Covered T4,T5,T6


LineNo. Expression -1-: 492 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 518 if ((!rst_ni)) -2-: 522 if (double_fault)

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T256,T257,T258
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 796 if (reg2hw.rnd_data.re) -2-: 800 if ((edn_req && edn_ack))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T123
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 808 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 15 68.18
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 15 68.18




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmIbexFetchEnable0_A 516738293 4 0 0
FpvSecCmIbexFetchEnable1_A 516738293 24966415 0 90
FpvSecCmIbexFetchEnable2_A 516738293 66251213 0 78
FpvSecCmIbexFetchEnable3Rev_A 516738293 445963857 0 2006
FpvSecCmIbexFetchEnable3_A 516738293 445965735 0 1904
FpvSecCmIbexInstrIntgErrCheck_A 516738293 77 0 0
FpvSecCmIbexLoadRespIntgErrCheck_A 516738293 589 0 0
FpvSecCmIbexLockstepResetCountAlertCheck_A 516738293 0 0 0
FpvSecCmIbexPcMismatchCheck_A 516738293 0 0 0
FpvSecCmIbexRfEccErrCheck_A 516738293 0 0 0
FpvSecCmIbexStoreRespIntgErrCheck_A 516738293 0 0 0
FpvSecCmRegWeOnehotCheck_A 516738293 2 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 516738293 0 0 0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 516738293 0 0 0
FpvSecCmRvCoreRegWeOnehotCheck_A 516738293 0 0 0
g_instr_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 1017 1017 0 0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 1017 1017 0 0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A 1017 1017 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 516738293 217 0 0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 516738293 203 0 0


FpvSecCmIbexFetchEnable0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 4 0 0
T107 155983 0 0 0
T256 225021 1 0 0
T257 0 1 0 0
T258 0 1 0 0
T275 0 1 0 0
T276 224936 0 0 0
T277 228529 0 0 0
T278 139768 0 0 0
T279 195890 0 0 0
T280 377536 0 0 0
T281 190818 0 0 0
T282 292046 0 0 0
T283 123371 0 0 0

FpvSecCmIbexFetchEnable1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 24966415 0 90
T4 278828 41066 0 0
T5 862854 10008 0 2
T6 204222 9923 0 0
T15 213648 9919 0 0
T16 152738 9931 0 0
T18 0 0 0 2
T44 199003 29831 0 0
T45 217490 19854 0 0
T57 0 0 0 2
T58 0 0 0 2
T67 0 0 0 2
T76 0 0 0 2
T86 0 0 0 2
T92 69384 9931 0 0
T93 90956 9923 0 0
T94 89313 9927 0 0
T188 0 0 0 2
T284 0 0 0 2
T285 0 0 0 2

FpvSecCmIbexFetchEnable2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 66251213 0 78
T4 278828 69555 0 0
T5 862854 34852 0 2
T6 204222 34775 0 0
T15 213648 34775 0 0
T16 152738 34775 0 0
T18 0 0 0 2
T19 0 0 0 2
T44 199003 104332 0 0
T45 217490 69555 0 0
T57 0 0 0 2
T58 0 0 0 2
T76 0 0 0 2
T86 0 0 0 2
T92 69384 34775 0 0
T93 90956 34775 0 0
T94 89313 34775 0 0
T188 0 0 0 2
T246 0 0 0 2
T285 0 0 0 2

FpvSecCmIbexFetchEnable3Rev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 445963857 0 2006
T4 278828 187939 0 2
T5 862854 827884 0 2
T6 204222 169393 0 2
T15 213648 178819 0 2
T16 152738 117902 0 2
T44 199003 94547 0 2
T45 217490 147817 0 2
T92 69384 34548 0 2
T93 90956 56123 0 2
T94 89313 54473 0 2

FpvSecCmIbexFetchEnable3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 445965735 0 1904
T4 278828 187941 0 2
T5 862854 827885 0 0
T6 204222 169394 0 2
T15 213648 178820 0 2
T16 152738 117903 0 2
T44 199003 94549 0 2
T45 217490 147818 0 2
T60 0 0 0 2
T92 69384 34549 0 2
T93 90956 56124 0 2
T94 89313 54474 0 2

FpvSecCmIbexInstrIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 77 0 0
T116 194414 0 0 0
T189 50214 0 0 0
T286 266855 77 0 0
T287 130715 0 0 0
T288 213494 0 0 0
T289 202198 0 0 0
T290 242051 0 0 0
T291 158619 0 0 0
T292 201989 0 0 0
T293 161250 0 0 0

FpvSecCmIbexLoadRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 589 0 0
T125 201546 32 0 0
T193 0 32 0 0
T225 158194 0 0 0
T255 258493 1 0 0
T265 79883 0 0 0
T294 0 32 0 0
T295 0 1 0 0
T296 0 100 0 0
T297 0 1 0 0
T298 0 1 0 0
T299 0 99 0 0
T300 0 32 0 0
T301 106720 0 0 0
T302 94215 0 0 0
T303 97738 0 0 0
T304 184272 0 0 0
T305 368700 0 0 0
T306 236175 0 0 0

FpvSecCmIbexLockstepResetCountAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexPcMismatchCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexRfEccErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmIbexStoreRespIntgErrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 2 0 0
T76 113290 0 0 0
T173 143288 0 0 0
T259 262146 1 0 0
T260 0 1 0 0
T267 196763 0 0 0
T274 54258 0 0 0
T307 134811 0 0 0
T308 260354 0 0 0
T309 160690 0 0 0
T310 93013 0 0 0
T311 517602 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

FpvSecCmRvCoreRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 0 0 0

g_instr_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1017 1017 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T92 1 1 0 0
T93 1 1 0 0
T94 1 1 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 217 0 0
T35 987089 0 0 0
T160 181409 0 0 0
T195 100189 33 0 0
T196 92365 36 0 0
T197 0 45 0 0
T312 0 33 0 0
T313 0 33 0 0
T314 0 37 0 0
T315 648058 0 0 0
T316 118042 0 0 0
T317 117075 0 0 0
T318 303251 0 0 0
T319 272002 0 0 0
T320 143633 0 0 0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 516738293 203 0 0
T26 606397 0 0 0
T55 118084 0 0 0
T113 268343 16 0 0
T114 92157 0 0 0
T124 63262 0 0 0
T172 246327 0 0 0
T194 0 16 0 0
T195 0 42 0 0
T196 0 9 0 0
T197 0 11 0 0
T312 0 42 0 0
T313 0 42 0 0
T314 0 9 0 0
T321 0 16 0 0
T322 198328 0 0 0
T323 204196 0 0 0
T324 133594 0 0 0
T325 281060 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%