Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T195,T9
0	1	Covered	T8,T195,T312
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T195,T312
1	1	Covered	T195,T312,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T195,T9
1	0	Covered	T195,T312,T313
1	1	Covered	T8,T195,T312

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T8,T195,T312

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1033476586	1015425540	0	0
CheckNGreaterZero_A	2034	2034	0	0
GntImpliesReady_A	1033476586	8381	0	0
GntImpliesValid_A	1033476586	8381	0	0
GrantKnown_A	1033476586	1015425540	0	0
IdxKnown_A	1033476586	1015425540	0	0
IndexIsCorrect_A	1033476586	8381	0	0
NoReadyValidNoGrant_A	1033476586	0	0	0
Priority_A	1033476586	8381	0	0
ReadyAndValidImplyGrant_A	1033476586	8381	0	0
ReqAndReadyImplyGrant_A	1033476586	8381	0	0
ReqImpliesValid_A	1033476586	8381	0	0
ValidKnown_A	1033476586	1015425540	0	0
gen_data_port_assertion.DataFlow_A	1033476586	8381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	1015425540	0	0
T4	557656	557422	0	0
T5	1725708	1725482	0	0
T6	408444	408342	0	0
T15	427296	427194	0	0
T16	305476	305360	0	0
T44	398006	397774	0	0
T45	434980	434754	0	0
T92	138768	138652	0	0
T93	181912	181802	0	0
T94	178626	178502	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2034	2034	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T44	2	2	0	0
T45	2	2	0	0
T92	2	2	0	0
T93	2	2	0	0
T94	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	1015425540	0	0
T4	557656	557422	0	0
T5	1725708	1725482	0	0
T6	408444	408342	0	0
T15	427296	427194	0	0
T16	305476	305360	0	0
T44	398006	397774	0	0
T45	434980	434754	0	0
T92	138768	138652	0	0
T93	181912	181802	0	0
T94	178626	178502	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	1015425540	0	0
T4	557656	557422	0	0
T5	1725708	1725482	0	0
T6	408444	408342	0	0
T15	427296	427194	0	0
T16	305476	305360	0	0
T44	398006	397774	0	0
T45	434980	434754	0	0
T92	138768	138652	0	0
T93	181912	181802	0	0
T94	178626	178502	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	1015425540	0	0
T4	557656	557422	0	0
T5	1725708	1725482	0	0
T6	408444	408342	0	0
T15	427296	427194	0	0
T16	305476	305360	0	0
T44	398006	397774	0	0
T45	434980	434754	0	0
T92	138768	138652	0	0
T93	181912	181802	0	0
T94	178626	178502	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033476586	8381	0	0
T35	1974178	0	0	0
T160	362818	0	0	0
T195	200378	2796	0	0
T196	184730	0	0	0
T312	0	2790	0	0
T313	0	2795	0	0
T315	1296116	0	0	0
T316	236084	0	0	0
T317	234150	0	0	0
T318	606502	0	0	0
T319	544004	0	0	0
T320	287266	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T195,T9
0	1	Covered	T195,T312,T313
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T195,T312,T313
1	1	Covered	T195,T312,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T195,T9
1	0	Covered	T195,T312,T313
1	1	Covered	T195,T312,T313

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T195,T312,T313

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	516738293	507712770	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	516738293	5192	0	0
GntImpliesValid_A	516738293	5192	0	0
GrantKnown_A	516738293	507712770	0	0
IdxKnown_A	516738293	507712770	0	0
IndexIsCorrect_A	516738293	5192	0	0
NoReadyValidNoGrant_A	516738293	0	0	0
Priority_A	516738293	5192	0	0
ReadyAndValidImplyGrant_A	516738293	5192	0	0
ReqAndReadyImplyGrant_A	516738293	5192	0	0
ReqImpliesValid_A	516738293	5192	0	0
ValidKnown_A	516738293	507712770	0	0
gen_data_port_assertion.DataFlow_A	516738293	5192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	5192	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1734	0	0
T196	92365	0	0	0
T312	0	1726	0	0
T313	0	1732	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T195,T9
0	1	Covered	T8,T195,T312
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T195,T312,T313
1	Covered	T8,T195,T9

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T195,T312
1	1	Covered	T195,T312,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T195,T9
1	0	Covered	T195,T312,T313
1	1	Covered	T8,T195,T312

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T8,T195,T312

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T195,T9
0	Covered	T195,T312,T313

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	516738293	507712770	0	0
CheckNGreaterZero_A	1017	1017	0	0
GntImpliesReady_A	516738293	3189	0	0
GntImpliesValid_A	516738293	3189	0	0
GrantKnown_A	516738293	507712770	0	0
IdxKnown_A	516738293	507712770	0	0
IndexIsCorrect_A	516738293	3189	0	0
NoReadyValidNoGrant_A	516738293	0	0	0
Priority_A	516738293	3189	0	0
ReadyAndValidImplyGrant_A	516738293	3189	0	0
ReqAndReadyImplyGrant_A	516738293	3189	0	0
ReqImpliesValid_A	516738293	3189	0	0
ValidKnown_A	516738293	507712770	0	0
gen_data_port_assertion.DataFlow_A	516738293	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T44	1	1	0	0
T45	1	1	0	0
T92	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	507712770	0	0
T4	278828	278711	0	0
T5	862854	862741	0	0
T6	204222	204171	0	0
T15	213648	213597	0	0
T16	152738	152680	0	0
T44	199003	198887	0	0
T45	217490	217377	0	0
T92	69384	69326	0	0
T93	90956	90901	0	0
T94	89313	89251	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516738293	3189	0	0
T35	987089	0	0	0
T160	181409	0	0	0
T195	100189	1062	0	0
T196	92365	0	0	0
T312	0	1064	0	0
T313	0	1063	0	0
T315	648058	0	0	0
T316	118042	0	0	0
T317	117075	0	0	0
T318	303251	0	0	0
T319	272002	0	0	0
T320	143633	0	0	0