Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 92.59 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sel_region 94.88 100.00 86.67 100.00 92.86



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 92.59 100.00 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sel_region 94.88 100.00 86.67 100.00 92.86

Line Coverage for Module : rv_core_addr_trans
Line No.TotalCoveredPercent
TOTAL7171100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 62 62
45 2 2
46 2 2
51 2 2
76 1 1
83 1 1
84 1 1


Cond Coverage for Module : rv_core_addr_trans
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT195,T9,T312
11CoveredT195,T312,T313

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT8,T195,T312
11CoveredT8,T195,T312

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T195,T312

Branch Coverage for Module : rv_core_addr_trans
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 76 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 (sel_match) ?

Branches:
-1-StatusTests
1 Covered T8,T195,T312
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans
Line No.TotalCoveredPercent
TOTAL7171100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 62 62
45 2 2
46 2 2
51 2 2
76 1 1
83 1 1
84 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT195,T312,T313
10CoveredT195,T9,T312
11CoveredT195,T312,T313

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT195,T312,T313

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT195,T312,T313
10CoveredT8,T195,T312
11CoveredT195,T312,T313

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT195,T312,T313

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT195,T312,T313

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 76 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 (sel_match) ?

Branches:
-1-StatusTests
1 Covered T195,T312,T313
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans
Line No.TotalCoveredPercent
TOTAL7171100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 62 62
45 2 2
46 2 2
51 2 2
76 1 1
83 1 1
84 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT195,T312,T313
11CoveredT195,T312,T313

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT8,T195,T312
11CoveredT8,T195,T312

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | (sel_region.remap_addr & (~sel_region.output_mask)))) : addr_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT8,T195,T312

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 76 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 76 (sel_match) ?

Branches:
-1-StatusTests
1 Covered T8,T195,T312
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%