| T391 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3917642635 |
|
|
Jul 07 07:26:39 PM PDT 24 |
Jul 07 07:30:09 PM PDT 24 |
2444388508 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.293052442 |
|
|
Jul 07 07:18:08 PM PDT 24 |
Jul 07 07:24:19 PM PDT 24 |
3106200666 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3507767719 |
|
|
Jul 07 07:19:16 PM PDT 24 |
Jul 07 07:31:45 PM PDT 24 |
4688397644 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_example_rom.1143368183 |
|
|
Jul 07 07:23:02 PM PDT 24 |
Jul 07 07:25:01 PM PDT 24 |
2133926330 ps |
| T747 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3117008233 |
|
|
Jul 07 07:26:32 PM PDT 24 |
Jul 07 07:28:17 PM PDT 24 |
2601107339 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2080121244 |
|
|
Jul 07 07:38:43 PM PDT 24 |
Jul 07 07:42:57 PM PDT 24 |
2728767282 ps |
| T128 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1758436022 |
|
|
Jul 07 07:19:06 PM PDT 24 |
Jul 07 07:30:26 PM PDT 24 |
4230631450 ps |
| T171 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.215305811 |
|
|
Jul 07 07:28:19 PM PDT 24 |
Jul 07 08:03:21 PM PDT 24 |
12496728900 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.606710540 |
|
|
Jul 07 07:31:21 PM PDT 24 |
Jul 07 08:01:44 PM PDT 24 |
8073231048 ps |
| T823 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2706614667 |
|
|
Jul 07 07:50:22 PM PDT 24 |
Jul 07 08:01:11 PM PDT 24 |
5914155686 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3892766308 |
|
|
Jul 07 07:32:09 PM PDT 24 |
Jul 07 07:38:41 PM PDT 24 |
4379513152 ps |
| T824 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.390062330 |
|
|
Jul 07 07:59:15 PM PDT 24 |
Jul 07 08:05:55 PM PDT 24 |
3522703878 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2137786815 |
|
|
Jul 07 07:34:46 PM PDT 24 |
Jul 07 07:54:37 PM PDT 24 |
7317076649 ps |
| T404 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.318768847 |
|
|
Jul 07 07:22:05 PM PDT 24 |
Jul 07 07:25:15 PM PDT 24 |
3116496100 ps |
| T1009 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2730646479 |
|
|
Jul 07 07:48:35 PM PDT 24 |
Jul 07 08:21:28 PM PDT 24 |
8985935792 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1724990629 |
|
|
Jul 07 07:31:19 PM PDT 24 |
Jul 07 07:43:15 PM PDT 24 |
5381240778 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.582563609 |
|
|
Jul 07 07:28:15 PM PDT 24 |
Jul 07 07:54:26 PM PDT 24 |
17154281839 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1890032323 |
|
|
Jul 07 07:20:03 PM PDT 24 |
Jul 07 11:05:55 PM PDT 24 |
254322256726 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.763290224 |
|
|
Jul 07 07:23:17 PM PDT 24 |
Jul 07 07:27:36 PM PDT 24 |
3398335862 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.991633482 |
|
|
Jul 07 07:39:22 PM PDT 24 |
Jul 07 07:48:21 PM PDT 24 |
3573910780 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1285063859 |
|
|
Jul 07 07:37:33 PM PDT 24 |
Jul 07 08:06:32 PM PDT 24 |
9451326520 ps |
| T1013 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1959723103 |
|
|
Jul 07 07:49:52 PM PDT 24 |
Jul 07 07:59:06 PM PDT 24 |
6266110801 ps |
| T893 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.697702557 |
|
|
Jul 07 07:51:03 PM PDT 24 |
Jul 07 07:56:44 PM PDT 24 |
3555114526 ps |
| T1014 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2381873256 |
|
|
Jul 07 07:50:39 PM PDT 24 |
Jul 07 08:01:28 PM PDT 24 |
3751340952 ps |
| T846 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.843499588 |
|
|
Jul 07 07:56:56 PM PDT 24 |
Jul 07 08:05:57 PM PDT 24 |
3528804682 ps |
| T138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3030483295 |
|
|
Jul 07 07:21:40 PM PDT 24 |
Jul 07 07:27:58 PM PDT 24 |
5586030926 ps |
| T748 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3864621674 |
|
|
Jul 07 07:27:59 PM PDT 24 |
Jul 07 07:29:37 PM PDT 24 |
2094739168 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3923241500 |
|
|
Jul 07 07:17:51 PM PDT 24 |
Jul 07 08:50:52 PM PDT 24 |
48930212901 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_power_idle_load.2202897273 |
|
|
Jul 07 07:23:26 PM PDT 24 |
Jul 07 07:37:59 PM PDT 24 |
4748685768 ps |
| T23 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.857498710 |
|
|
Jul 07 07:36:23 PM PDT 24 |
Jul 07 07:46:11 PM PDT 24 |
4280759113 ps |
| T797 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2610995650 |
|
|
Jul 07 07:49:02 PM PDT 24 |
Jul 07 07:55:51 PM PDT 24 |
3883905896 ps |
| T1015 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2311011646 |
|
|
Jul 07 07:54:08 PM PDT 24 |
Jul 07 08:01:53 PM PDT 24 |
4202102092 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.648594504 |
|
|
Jul 07 07:25:19 PM PDT 24 |
Jul 07 07:37:02 PM PDT 24 |
5776782080 ps |
| T189 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2472799592 |
|
|
Jul 07 07:18:19 PM PDT 24 |
Jul 07 07:20:59 PM PDT 24 |
2775513650 ps |
| T287 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1483053429 |
|
|
Jul 07 07:28:09 PM PDT 24 |
Jul 07 08:47:47 PM PDT 24 |
15445292260 ps |
| T288 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2153981156 |
|
|
Jul 07 07:49:24 PM PDT 24 |
Jul 07 07:59:38 PM PDT 24 |
6662408393 ps |
| T116 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3564746305 |
|
|
Jul 07 07:28:57 PM PDT 24 |
Jul 07 07:43:18 PM PDT 24 |
20431541860 ps |
| T289 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1370570024 |
|
|
Jul 07 07:26:04 PM PDT 24 |
Jul 07 09:11:27 PM PDT 24 |
22624918444 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.515216240 |
|
|
Jul 07 07:19:23 PM PDT 24 |
Jul 07 07:34:58 PM PDT 24 |
4257433736 ps |
| T291 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2195579047 |
|
|
Jul 07 07:52:44 PM PDT 24 |
Jul 07 07:59:37 PM PDT 24 |
3919723128 ps |
| T292 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.656462052 |
|
|
Jul 07 07:48:58 PM PDT 24 |
Jul 07 09:10:07 PM PDT 24 |
21233695600 ps |
| T293 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1859169667 |
|
|
Jul 07 07:56:12 PM PDT 24 |
Jul 07 08:05:59 PM PDT 24 |
3633634584 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2668505927 |
|
|
Jul 07 07:20:44 PM PDT 24 |
Jul 07 07:32:22 PM PDT 24 |
6582618098 ps |
| T1017 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.261658685 |
|
|
Jul 07 07:32:49 PM PDT 24 |
Jul 07 07:45:46 PM PDT 24 |
8685115240 ps |
| T1018 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.2045769465 |
|
|
Jul 07 07:40:23 PM PDT 24 |
Jul 07 08:52:32 PM PDT 24 |
15622373464 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.518911591 |
|
|
Jul 07 07:18:27 PM PDT 24 |
Jul 07 07:36:30 PM PDT 24 |
5167832240 ps |
| T757 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.801043926 |
|
|
Jul 07 07:38:53 PM PDT 24 |
Jul 07 07:43:21 PM PDT 24 |
2902444392 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1231819584 |
|
|
Jul 07 07:34:18 PM PDT 24 |
Jul 07 08:55:51 PM PDT 24 |
16543515948 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2515897865 |
|
|
Jul 07 07:17:17 PM PDT 24 |
Jul 07 07:22:03 PM PDT 24 |
2548359500 ps |
| T1021 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1404530180 |
|
|
Jul 07 07:47:18 PM PDT 24 |
Jul 07 07:57:58 PM PDT 24 |
5707566599 ps |
| T428 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2306956679 |
|
|
Jul 07 07:52:36 PM PDT 24 |
Jul 07 08:02:53 PM PDT 24 |
5923661180 ps |
| T429 |
/workspace/coverage/default/1.chip_tap_straps_prod.2438914249 |
|
|
Jul 07 07:32:52 PM PDT 24 |
Jul 07 07:52:47 PM PDT 24 |
10456938122 ps |
| T430 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3678643262 |
|
|
Jul 07 07:38:30 PM PDT 24 |
Jul 07 08:11:34 PM PDT 24 |
18963466442 ps |
| T431 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1509989961 |
|
|
Jul 07 07:29:58 PM PDT 24 |
Jul 07 07:36:50 PM PDT 24 |
4511897560 ps |
| T432 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1803123376 |
|
|
Jul 07 07:52:27 PM PDT 24 |
Jul 07 08:02:59 PM PDT 24 |
4161350632 ps |
| T433 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150944792 |
|
|
Jul 07 07:56:48 PM PDT 24 |
Jul 07 08:03:38 PM PDT 24 |
4260038608 ps |
| T434 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1396352533 |
|
|
Jul 07 07:26:46 PM PDT 24 |
Jul 07 09:12:35 PM PDT 24 |
23255291791 ps |
| T435 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1377680866 |
|
|
Jul 07 07:49:34 PM PDT 24 |
Jul 07 08:02:51 PM PDT 24 |
12411361535 ps |
| T436 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698874002 |
|
|
Jul 07 07:53:03 PM PDT 24 |
Jul 07 07:58:39 PM PDT 24 |
3630038296 ps |
| T88 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1197902880 |
|
|
Jul 07 07:16:42 PM PDT 24 |
Jul 07 07:38:06 PM PDT 24 |
10446346552 ps |
| T194 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3992745691 |
|
|
Jul 07 07:31:09 PM PDT 24 |
Jul 07 07:45:05 PM PDT 24 |
9872427535 ps |
| T64 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1310314295 |
|
|
Jul 07 07:33:42 PM PDT 24 |
Jul 07 07:55:56 PM PDT 24 |
19522777580 ps |
| T1022 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2777402123 |
|
|
Jul 07 07:29:55 PM PDT 24 |
Jul 07 07:35:49 PM PDT 24 |
5767535832 ps |
| T1023 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.499804013 |
|
|
Jul 07 07:39:29 PM PDT 24 |
Jul 07 07:59:16 PM PDT 24 |
6699063131 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3196889520 |
|
|
Jul 07 07:26:49 PM PDT 24 |
Jul 07 08:56:42 PM PDT 24 |
49109581664 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4292466028 |
|
|
Jul 07 07:17:42 PM PDT 24 |
Jul 07 09:26:50 PM PDT 24 |
31989914876 ps |
| T806 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2107169045 |
|
|
Jul 07 07:52:41 PM PDT 24 |
Jul 07 07:59:07 PM PDT 24 |
3466472008 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3556048190 |
|
|
Jul 07 07:26:45 PM PDT 24 |
Jul 07 07:34:27 PM PDT 24 |
4417419952 ps |
| T1025 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1581267334 |
|
|
Jul 07 07:40:14 PM PDT 24 |
Jul 07 08:04:33 PM PDT 24 |
6606801656 ps |
| T876 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.429747014 |
|
|
Jul 07 07:55:47 PM PDT 24 |
Jul 07 08:05:28 PM PDT 24 |
4619312040 ps |
| T105 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2337478195 |
|
|
Jul 07 07:20:25 PM PDT 24 |
Jul 07 07:48:57 PM PDT 24 |
21406985170 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2717713508 |
|
|
Jul 07 07:22:54 PM PDT 24 |
Jul 07 07:27:44 PM PDT 24 |
3418262992 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1302802345 |
|
|
Jul 07 07:16:47 PM PDT 24 |
Jul 07 08:53:32 PM PDT 24 |
26486512850 ps |
| T1028 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.122227793 |
|
|
Jul 07 07:51:00 PM PDT 24 |
Jul 07 08:06:56 PM PDT 24 |
12392390725 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2864537701 |
|
|
Jul 07 07:18:52 PM PDT 24 |
Jul 07 07:28:44 PM PDT 24 |
6948389865 ps |
| T1030 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.949841023 |
|
|
Jul 07 07:49:30 PM PDT 24 |
Jul 07 08:31:11 PM PDT 24 |
13420378600 ps |
| T78 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.2799301390 |
|
|
Jul 07 07:43:54 PM PDT 24 |
Jul 07 07:48:17 PM PDT 24 |
3288258298 ps |
| T1031 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1895390360 |
|
|
Jul 07 07:17:17 PM PDT 24 |
Jul 07 07:31:38 PM PDT 24 |
6382261208 ps |
| T1032 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1950672001 |
|
|
Jul 07 07:41:51 PM PDT 24 |
Jul 07 08:44:50 PM PDT 24 |
14697869872 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3511111693 |
|
|
Jul 07 07:35:43 PM PDT 24 |
Jul 07 07:42:24 PM PDT 24 |
2677175527 ps |
| T1034 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.767334036 |
|
|
Jul 07 07:58:36 PM PDT 24 |
Jul 07 08:08:14 PM PDT 24 |
5590834792 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2929594414 |
|
|
Jul 07 07:44:39 PM PDT 24 |
Jul 07 08:05:36 PM PDT 24 |
7258687886 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1055882203 |
|
|
Jul 07 07:25:36 PM PDT 24 |
Jul 07 07:37:58 PM PDT 24 |
5000574552 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1341515539 |
|
|
Jul 07 07:18:24 PM PDT 24 |
Jul 07 07:31:13 PM PDT 24 |
4891272520 ps |
| T1037 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2555358531 |
|
|
Jul 07 07:49:47 PM PDT 24 |
Jul 07 08:06:12 PM PDT 24 |
12621647246 ps |
| T1038 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4081575588 |
|
|
Jul 07 07:28:14 PM PDT 24 |
Jul 07 08:41:34 PM PDT 24 |
15599362504 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3289272488 |
|
|
Jul 07 07:28:09 PM PDT 24 |
Jul 07 07:38:31 PM PDT 24 |
4761512819 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.932069762 |
|
|
Jul 07 07:25:21 PM PDT 24 |
Jul 07 08:56:58 PM PDT 24 |
43242991323 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3703900192 |
|
|
Jul 07 07:30:47 PM PDT 24 |
Jul 07 07:35:49 PM PDT 24 |
3254674864 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2544122578 |
|
|
Jul 07 07:31:37 PM PDT 24 |
Jul 07 07:35:13 PM PDT 24 |
2617194190 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.629037642 |
|
|
Jul 07 07:42:04 PM PDT 24 |
Jul 07 07:51:51 PM PDT 24 |
5294593400 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.131690045 |
|
|
Jul 07 07:19:01 PM PDT 24 |
Jul 07 07:40:21 PM PDT 24 |
6307835352 ps |
| T249 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1888822759 |
|
|
Jul 07 07:39:21 PM PDT 24 |
Jul 07 09:05:08 PM PDT 24 |
47083980484 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.201652689 |
|
|
Jul 07 07:41:43 PM PDT 24 |
Jul 07 07:53:27 PM PDT 24 |
4609495816 ps |
| T1041 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3092154542 |
|
|
Jul 07 07:47:19 PM PDT 24 |
Jul 07 07:56:16 PM PDT 24 |
5497374588 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3456813592 |
|
|
Jul 07 07:17:25 PM PDT 24 |
Jul 07 07:43:45 PM PDT 24 |
11949579048 ps |
| T1042 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3909903193 |
|
|
Jul 07 07:24:47 PM PDT 24 |
Jul 07 09:05:52 PM PDT 24 |
22642437928 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1265230599 |
|
|
Jul 07 07:23:46 PM PDT 24 |
Jul 07 08:11:26 PM PDT 24 |
33450133576 ps |
| T859 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.656661983 |
|
|
Jul 07 07:55:17 PM PDT 24 |
Jul 07 08:05:48 PM PDT 24 |
5019397318 ps |
| T851 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476794802 |
|
|
Jul 07 07:54:25 PM PDT 24 |
Jul 07 08:02:34 PM PDT 24 |
3450138924 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3180724423 |
|
|
Jul 07 07:47:33 PM PDT 24 |
Jul 07 07:51:34 PM PDT 24 |
2965155112 ps |
| T89 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2845812038 |
|
|
Jul 07 07:29:57 PM PDT 24 |
Jul 07 07:35:27 PM PDT 24 |
3245146956 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1664876269 |
|
|
Jul 07 07:18:52 PM PDT 24 |
Jul 07 07:28:18 PM PDT 24 |
4589553560 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3300187740 |
|
|
Jul 07 07:37:30 PM PDT 24 |
Jul 07 07:43:12 PM PDT 24 |
3416024930 ps |
| T796 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3994599435 |
|
|
Jul 07 07:55:51 PM PDT 24 |
Jul 07 08:03:26 PM PDT 24 |
3881736940 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1916146851 |
|
|
Jul 07 07:24:18 PM PDT 24 |
Jul 07 07:34:36 PM PDT 24 |
18079629880 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3029885204 |
|
|
Jul 07 07:33:51 PM PDT 24 |
Jul 07 07:46:33 PM PDT 24 |
3827639014 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1082286058 |
|
|
Jul 07 07:17:40 PM PDT 24 |
Jul 07 08:27:34 PM PDT 24 |
14502597630 ps |
| T1046 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.309791505 |
|
|
Jul 07 07:36:48 PM PDT 24 |
Jul 07 07:41:24 PM PDT 24 |
2283163440 ps |
| T393 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2366358610 |
|
|
Jul 07 07:17:37 PM PDT 24 |
Jul 07 07:29:38 PM PDT 24 |
6311224295 ps |
| T807 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4142806697 |
|
|
Jul 07 07:50:36 PM PDT 24 |
Jul 07 07:57:34 PM PDT 24 |
3201664676 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.785726728 |
|
|
Jul 07 07:46:22 PM PDT 24 |
Jul 07 07:51:41 PM PDT 24 |
3369156385 ps |
| T1047 |
/workspace/coverage/default/1.rom_e2e_static_critical.4266986682 |
|
|
Jul 07 07:39:30 PM PDT 24 |
Jul 07 08:57:15 PM PDT 24 |
16881918580 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3155317501 |
|
|
Jul 07 07:18:05 PM PDT 24 |
Jul 07 07:37:08 PM PDT 24 |
10591267207 ps |
| T1049 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.362156658 |
|
|
Jul 07 07:17:58 PM PDT 24 |
Jul 07 07:39:41 PM PDT 24 |
10852786578 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2840659106 |
|
|
Jul 07 07:20:18 PM PDT 24 |
Jul 07 07:25:07 PM PDT 24 |
2987338584 ps |
| T1051 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3867651370 |
|
|
Jul 07 07:51:10 PM PDT 24 |
Jul 07 08:48:12 PM PDT 24 |
15831078937 ps |
| T749 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1145800672 |
|
|
Jul 07 07:36:36 PM PDT 24 |
Jul 07 07:38:25 PM PDT 24 |
2063829903 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2528774900 |
|
|
Jul 07 07:19:18 PM PDT 24 |
Jul 07 07:23:15 PM PDT 24 |
3158079324 ps |
| T339 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.677424708 |
|
|
Jul 07 07:30:19 PM PDT 24 |
Jul 07 07:54:54 PM PDT 24 |
6063038316 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3710708895 |
|
|
Jul 07 07:21:32 PM PDT 24 |
Jul 07 10:42:03 PM PDT 24 |
65987963120 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1681843400 |
|
|
Jul 07 07:40:32 PM PDT 24 |
Jul 07 08:04:18 PM PDT 24 |
5096788200 ps |
| T758 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3399128426 |
|
|
Jul 07 07:28:10 PM PDT 24 |
Jul 07 07:32:19 PM PDT 24 |
2917307276 ps |
| T1054 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1595391925 |
|
|
Jul 07 07:37:25 PM PDT 24 |
Jul 07 07:49:08 PM PDT 24 |
4503365278 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.703588158 |
|
|
Jul 07 07:44:19 PM PDT 24 |
Jul 07 07:54:23 PM PDT 24 |
5973446728 ps |
| T443 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2371513240 |
|
|
Jul 07 07:30:32 PM PDT 24 |
Jul 07 08:00:00 PM PDT 24 |
8420043180 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.445491176 |
|
|
Jul 07 07:42:49 PM PDT 24 |
Jul 07 08:28:44 PM PDT 24 |
25056877840 ps |
| T1057 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.709401451 |
|
|
Jul 07 07:46:44 PM PDT 24 |
Jul 07 07:56:04 PM PDT 24 |
4240242536 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.557394420 |
|
|
Jul 07 07:29:42 PM PDT 24 |
Jul 07 07:48:38 PM PDT 24 |
9682529486 ps |
| T1058 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.4179876478 |
|
|
Jul 07 07:45:41 PM PDT 24 |
Jul 07 07:56:18 PM PDT 24 |
5470324794 ps |
| T808 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906046614 |
|
|
Jul 07 07:56:13 PM PDT 24 |
Jul 07 08:04:56 PM PDT 24 |
4254738336 ps |
| T813 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3990630317 |
|
|
Jul 07 07:53:20 PM PDT 24 |
Jul 07 08:01:55 PM PDT 24 |
4671946136 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3343099092 |
|
|
Jul 07 07:31:38 PM PDT 24 |
Jul 07 07:37:09 PM PDT 24 |
2684713904 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3489524799 |
|
|
Jul 07 07:19:15 PM PDT 24 |
Jul 07 07:31:26 PM PDT 24 |
4364741712 ps |
| T359 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3611141947 |
|
|
Jul 07 07:54:55 PM PDT 24 |
Jul 07 08:04:53 PM PDT 24 |
4772067336 ps |
| T870 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246162515 |
|
|
Jul 07 07:50:40 PM PDT 24 |
Jul 07 07:58:55 PM PDT 24 |
4678937104 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.864233277 |
|
|
Jul 07 07:46:04 PM PDT 24 |
Jul 07 07:50:35 PM PDT 24 |
2695729757 ps |
| T1062 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2708077344 |
|
|
Jul 07 07:27:39 PM PDT 24 |
Jul 07 09:19:12 PM PDT 24 |
23360932062 ps |
| T891 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.953141429 |
|
|
Jul 07 07:52:17 PM PDT 24 |
Jul 07 07:59:55 PM PDT 24 |
4470282280 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3155973174 |
|
|
Jul 07 07:41:45 PM PDT 24 |
Jul 07 07:45:08 PM PDT 24 |
2773373656 ps |
| T792 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238245748 |
|
|
Jul 07 07:56:23 PM PDT 24 |
Jul 07 08:03:51 PM PDT 24 |
3790939160 ps |
| T860 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975303548 |
|
|
Jul 07 07:56:27 PM PDT 24 |
Jul 07 08:03:06 PM PDT 24 |
3629213900 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4262699442 |
|
|
Jul 07 07:45:35 PM PDT 24 |
Jul 07 07:51:57 PM PDT 24 |
4071740644 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2948306003 |
|
|
Jul 07 07:25:43 PM PDT 24 |
Jul 07 07:33:13 PM PDT 24 |
3177559736 ps |
| T1065 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.674029242 |
|
|
Jul 07 07:30:14 PM PDT 24 |
Jul 07 07:49:28 PM PDT 24 |
5662583288 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4042893062 |
|
|
Jul 07 07:18:47 PM PDT 24 |
Jul 07 07:30:55 PM PDT 24 |
4971923330 ps |
| T1066 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1371292297 |
|
|
Jul 07 07:50:42 PM PDT 24 |
Jul 07 08:51:37 PM PDT 24 |
14844361880 ps |
| T1067 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4273181819 |
|
|
Jul 07 07:48:36 PM PDT 24 |
Jul 07 07:55:28 PM PDT 24 |
7535498832 ps |
| T744 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1307585731 |
|
|
Jul 07 07:43:59 PM PDT 24 |
Jul 07 07:54:26 PM PDT 24 |
5538157713 ps |
| T1068 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1759151361 |
|
|
Jul 07 07:40:34 PM PDT 24 |
Jul 07 07:50:13 PM PDT 24 |
18542215920 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1889164898 |
|
|
Jul 07 07:25:30 PM PDT 24 |
Jul 07 07:30:05 PM PDT 24 |
3029198944 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_edn_kat.1461960803 |
|
|
Jul 07 07:17:45 PM PDT 24 |
Jul 07 07:28:21 PM PDT 24 |
3519547678 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1772128134 |
|
|
Jul 07 07:19:14 PM PDT 24 |
Jul 07 07:29:01 PM PDT 24 |
3870081700 ps |
| T1071 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1370045693 |
|
|
Jul 07 07:50:30 PM PDT 24 |
Jul 07 08:06:06 PM PDT 24 |
10630444040 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.379942799 |
|
|
Jul 07 07:29:03 PM PDT 24 |
Jul 07 08:01:24 PM PDT 24 |
20936841414 ps |
| T829 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2969219157 |
|
|
Jul 07 07:51:04 PM PDT 24 |
Jul 07 08:03:43 PM PDT 24 |
5009360446 ps |
| T381 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.41602562 |
|
|
Jul 07 07:56:20 PM PDT 24 |
Jul 07 08:02:27 PM PDT 24 |
3222275480 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3665978883 |
|
|
Jul 07 07:30:07 PM PDT 24 |
Jul 07 11:15:23 PM PDT 24 |
255426707734 ps |
| T384 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1592914764 |
|
|
Jul 07 07:18:03 PM PDT 24 |
Jul 07 07:28:45 PM PDT 24 |
5416865336 ps |
| T295 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.974000678 |
|
|
Jul 07 07:17:50 PM PDT 24 |
Jul 07 07:28:27 PM PDT 24 |
4212805000 ps |
| T385 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1969954649 |
|
|
Jul 07 07:57:38 PM PDT 24 |
Jul 07 08:06:13 PM PDT 24 |
4303961574 ps |
| T386 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.681132159 |
|
|
Jul 07 07:26:49 PM PDT 24 |
Jul 07 08:59:15 PM PDT 24 |
17295184747 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_flash_init.2082525739 |
|
|
Jul 07 07:25:50 PM PDT 24 |
Jul 07 08:05:42 PM PDT 24 |
23164864409 ps |
| T387 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2916908527 |
|
|
Jul 07 07:39:34 PM PDT 24 |
Jul 07 07:54:05 PM PDT 24 |
8685419158 ps |
| T388 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3613583467 |
|
|
Jul 07 07:25:52 PM PDT 24 |
Jul 07 08:39:06 PM PDT 24 |
14182713451 ps |
| T389 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3651956548 |
|
|
Jul 07 07:19:42 PM PDT 24 |
Jul 07 07:27:14 PM PDT 24 |
4194569192 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1669617899 |
|
|
Jul 07 07:22:16 PM PDT 24 |
Jul 07 08:33:39 PM PDT 24 |
21042162190 ps |
| T1072 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2926487310 |
|
|
Jul 07 07:46:14 PM PDT 24 |
Jul 07 07:50:07 PM PDT 24 |
2805325680 ps |
| T1073 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2557721607 |
|
|
Jul 07 07:47:30 PM PDT 24 |
Jul 07 07:59:06 PM PDT 24 |
4506135810 ps |
| T873 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2355514694 |
|
|
Jul 07 07:59:45 PM PDT 24 |
Jul 07 08:07:25 PM PDT 24 |
3825328200 ps |
| T1074 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1189013584 |
|
|
Jul 07 07:28:23 PM PDT 24 |
Jul 07 08:46:39 PM PDT 24 |
15609315560 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.100268446 |
|
|
Jul 07 07:29:09 PM PDT 24 |
Jul 07 09:09:59 PM PDT 24 |
45696261976 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2227117326 |
|
|
Jul 07 07:42:20 PM PDT 24 |
Jul 07 07:46:11 PM PDT 24 |
2909847932 ps |
| T1076 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3370292641 |
|
|
Jul 07 07:40:17 PM PDT 24 |
Jul 07 08:55:13 PM PDT 24 |
15521860453 ps |
| T296 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.890840717 |
|
|
Jul 07 07:39:47 PM PDT 24 |
Jul 07 07:48:40 PM PDT 24 |
3829772776 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.932694757 |
|
|
Jul 07 07:29:16 PM PDT 24 |
Jul 07 07:40:35 PM PDT 24 |
6979465000 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3874594598 |
|
|
Jul 07 07:18:39 PM PDT 24 |
Jul 07 07:28:53 PM PDT 24 |
4129862682 ps |
| T335 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.556913092 |
|
|
Jul 07 07:33:50 PM PDT 24 |
Jul 07 07:57:54 PM PDT 24 |
6311111198 ps |
| T1077 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2725220285 |
|
|
Jul 07 07:50:55 PM PDT 24 |
Jul 07 08:03:05 PM PDT 24 |
6810165578 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2024626455 |
|
|
Jul 07 07:25:36 PM PDT 24 |
Jul 07 07:37:33 PM PDT 24 |
4496416399 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4238028639 |
|
|
Jul 07 07:32:59 PM PDT 24 |
Jul 07 07:39:39 PM PDT 24 |
4942449081 ps |
| T892 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.22341822 |
|
|
Jul 07 07:58:10 PM PDT 24 |
Jul 07 08:05:51 PM PDT 24 |
3316659316 ps |
| T1080 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2009046120 |
|
|
Jul 07 07:40:08 PM PDT 24 |
Jul 07 08:01:16 PM PDT 24 |
8131020100 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.974712658 |
|
|
Jul 07 07:42:51 PM PDT 24 |
Jul 07 07:47:55 PM PDT 24 |
2589503320 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2683210327 |
|
|
Jul 07 07:49:10 PM PDT 24 |
Jul 07 07:52:52 PM PDT 24 |
3031360000 ps |
| T119 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.873018384 |
|
|
Jul 07 07:21:26 PM PDT 24 |
Jul 07 08:44:15 PM PDT 24 |
21977826067 ps |
| T260 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1996374324 |
|
|
Jul 07 07:51:14 PM PDT 24 |
Jul 07 08:05:27 PM PDT 24 |
4620238372 ps |
| T1083 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2847667915 |
|
|
Jul 07 07:17:25 PM PDT 24 |
Jul 07 07:21:58 PM PDT 24 |
2944122312 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2664298278 |
|
|
Jul 07 07:20:12 PM PDT 24 |
Jul 07 07:27:43 PM PDT 24 |
5177825800 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3816922414 |
|
|
Jul 07 07:31:57 PM PDT 24 |
Jul 07 08:21:39 PM PDT 24 |
12363568668 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3269815737 |
|
|
Jul 07 07:19:18 PM PDT 24 |
Jul 07 07:44:25 PM PDT 24 |
8339085438 ps |
| T427 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3132685462 |
|
|
Jul 07 07:24:23 PM PDT 24 |
Jul 07 08:14:19 PM PDT 24 |
24734927150 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.157109238 |
|
|
Jul 07 07:22:24 PM PDT 24 |
Jul 07 07:26:50 PM PDT 24 |
4357304276 ps |
| T1087 |
/workspace/coverage/default/0.rom_e2e_static_critical.335093492 |
|
|
Jul 07 07:27:07 PM PDT 24 |
Jul 07 08:51:07 PM PDT 24 |
16980091104 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4079936251 |
|
|
Jul 07 07:20:16 PM PDT 24 |
Jul 07 07:34:29 PM PDT 24 |
9060643260 ps |
| T297 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1287365383 |
|
|
Jul 07 07:48:43 PM PDT 24 |
Jul 07 08:05:01 PM PDT 24 |
6175243120 ps |
| T344 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.71958153 |
|
|
Jul 07 07:37:58 PM PDT 24 |
Jul 07 07:48:18 PM PDT 24 |
3762519560 ps |
| T880 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.87164617 |
|
|
Jul 07 07:52:56 PM PDT 24 |
Jul 07 07:58:26 PM PDT 24 |
4120629664 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1419601457 |
|
|
Jul 07 07:44:11 PM PDT 24 |
Jul 07 07:52:12 PM PDT 24 |
7761419774 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3741017023 |
|
|
Jul 07 07:45:58 PM PDT 24 |
Jul 07 08:55:40 PM PDT 24 |
24699394108 ps |
| T790 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1473569212 |
|
|
Jul 07 07:55:43 PM PDT 24 |
Jul 07 08:01:28 PM PDT 24 |
3634739340 ps |
| T1090 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1799796445 |
|
|
Jul 07 07:39:09 PM PDT 24 |
Jul 07 08:42:29 PM PDT 24 |
14467939940 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3689250793 |
|
|
Jul 07 07:25:45 PM PDT 24 |
Jul 07 07:34:19 PM PDT 24 |
3507388776 ps |
| T79 |
/workspace/coverage/default/1.chip_tap_straps_rma.2317611933 |
|
|
Jul 07 07:34:52 PM PDT 24 |
Jul 07 07:40:36 PM PDT 24 |
4227957261 ps |
| T394 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.680274468 |
|
|
Jul 07 07:29:32 PM PDT 24 |
Jul 07 07:37:46 PM PDT 24 |
3051790200 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2305383860 |
|
|
Jul 07 07:20:16 PM PDT 24 |
Jul 07 08:32:12 PM PDT 24 |
25071777528 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2886801886 |
|
|
Jul 07 07:23:53 PM PDT 24 |
Jul 07 07:36:07 PM PDT 24 |
6001292640 ps |
| T769 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2841669686 |
|
|
Jul 07 07:18:46 PM PDT 24 |
Jul 07 07:25:18 PM PDT 24 |
3382242612 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3676103271 |
|
|
Jul 07 07:18:22 PM PDT 24 |
Jul 07 07:35:57 PM PDT 24 |
4276817684 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2208419079 |
|
|
Jul 07 07:18:02 PM PDT 24 |
Jul 07 07:23:22 PM PDT 24 |
3263125540 ps |
| T1095 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2033781687 |
|
|
Jul 07 07:33:12 PM PDT 24 |
Jul 07 07:41:35 PM PDT 24 |
3585520688 ps |
| T298 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1880230474 |
|
|
Jul 07 07:36:23 PM PDT 24 |
Jul 07 07:49:47 PM PDT 24 |
6239900292 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.157341661 |
|
|
Jul 07 07:29:06 PM PDT 24 |
Jul 07 07:35:57 PM PDT 24 |
3688739532 ps |
| T70 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2407355212 |
|
|
Jul 07 07:19:04 PM PDT 24 |
Jul 07 07:22:45 PM PDT 24 |
2703742525 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1412585335 |
|
|
Jul 07 07:36:24 PM PDT 24 |
Jul 07 07:41:51 PM PDT 24 |
2753330600 ps |
| T1097 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.118833272 |
|
|
Jul 07 07:53:08 PM PDT 24 |
Jul 07 08:04:37 PM PDT 24 |
6761271352 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1835935888 |
|
|
Jul 07 07:38:48 PM PDT 24 |
Jul 07 07:47:35 PM PDT 24 |
4269405960 ps |
| T867 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.478620633 |
|
|
Jul 07 07:57:14 PM PDT 24 |
Jul 07 08:08:46 PM PDT 24 |
5693765340 ps |
| T868 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2242365929 |
|
|
Jul 07 08:00:08 PM PDT 24 |
Jul 07 08:06:55 PM PDT 24 |
3637148502 ps |
| T1098 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3612893842 |
|
|
Jul 07 07:18:06 PM PDT 24 |
Jul 07 07:25:40 PM PDT 24 |
4400616552 ps |
| T750 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2123760871 |
|
|
Jul 07 07:38:56 PM PDT 24 |
Jul 07 07:40:35 PM PDT 24 |
2195656701 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2763735753 |
|
|
Jul 07 07:36:24 PM PDT 24 |
Jul 07 09:01:05 PM PDT 24 |
43444008720 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1678751656 |
|
|
Jul 07 07:44:38 PM PDT 24 |
Jul 07 07:56:37 PM PDT 24 |
4453151894 ps |
| T1100 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3466754694 |
|
|
Jul 07 07:50:06 PM PDT 24 |
Jul 07 08:00:04 PM PDT 24 |
4384141163 ps |
| T809 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975693836 |
|
|
Jul 07 07:59:08 PM PDT 24 |
Jul 07 08:07:01 PM PDT 24 |
3840730560 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1389714849 |
|
|
Jul 07 07:38:32 PM PDT 24 |
Jul 07 07:44:29 PM PDT 24 |
3823878416 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2664423292 |
|
|
Jul 07 07:45:04 PM PDT 24 |
Jul 07 08:35:52 PM PDT 24 |
11676963034 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2717129629 |
|
|
Jul 07 07:39:38 PM PDT 24 |
Jul 07 07:51:57 PM PDT 24 |
4135662623 ps |
| T1101 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1559688853 |
|
|
Jul 07 07:49:49 PM PDT 24 |
Jul 07 08:58:12 PM PDT 24 |
14776350632 ps |
| T63 |
/workspace/coverage/default/0.chip_sw_alert_test.4250563468 |
|
|
Jul 07 07:20:43 PM PDT 24 |
Jul 07 07:27:46 PM PDT 24 |
2789245084 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1610531342 |
|
|
Jul 07 07:47:18 PM PDT 24 |
Jul 07 07:53:08 PM PDT 24 |
3555982208 ps |
| T315 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3059001345 |
|
|
Jul 07 07:30:55 PM PDT 24 |
Jul 07 08:03:53 PM PDT 24 |
9210981048 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.380085683 |
|
|
Jul 07 07:28:47 PM PDT 24 |
Jul 07 08:11:33 PM PDT 24 |
23596301935 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2773853749 |
|
|
Jul 07 07:20:10 PM PDT 24 |
Jul 07 07:27:41 PM PDT 24 |
2736852057 ps |
| T318 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2014577593 |
|
|
Jul 07 07:19:42 PM PDT 24 |
Jul 07 07:36:10 PM PDT 24 |
6313059168 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2840843993 |
|
|
Jul 07 07:19:30 PM PDT 24 |
Jul 07 08:11:05 PM PDT 24 |
12059547028 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.932468184 |
|
|
Jul 07 07:17:22 PM PDT 24 |
Jul 07 07:26:53 PM PDT 24 |
3764411080 ps |
| T319 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2290778758 |
|
|
Jul 07 07:41:36 PM PDT 24 |
Jul 07 07:55:32 PM PDT 24 |
5054245640 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3986929728 |
|
|
Jul 07 07:22:47 PM PDT 24 |
Jul 07 07:28:08 PM PDT 24 |
2505344753 ps |
| T320 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3595303417 |
|
|
Jul 07 07:54:58 PM PDT 24 |
Jul 07 08:02:24 PM PDT 24 |
3470295820 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1916147973 |
|
|
Jul 07 07:44:16 PM PDT 24 |
Jul 07 07:49:10 PM PDT 24 |
2978557516 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3559479432 |
|
|
Jul 07 07:17:16 PM PDT 24 |
Jul 07 08:42:41 PM PDT 24 |
43792296004 ps |
| T214 |
/workspace/coverage/default/2.chip_jtag_csr_rw.3749377043 |
|
|
Jul 07 07:36:46 PM PDT 24 |
Jul 07 08:01:17 PM PDT 24 |
12512802260 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2139254054 |
|
|
Jul 07 07:39:17 PM PDT 24 |
Jul 07 08:15:12 PM PDT 24 |
32436610912 ps |
| T1104 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2492798598 |
|
|
Jul 07 07:41:02 PM PDT 24 |
Jul 07 09:04:05 PM PDT 24 |
14872824696 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.201047145 |
|
|
Jul 07 07:39:42 PM PDT 24 |
Jul 07 08:00:17 PM PDT 24 |
5495402604 ps |
| T874 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1604236713 |
|
|
Jul 07 07:52:36 PM PDT 24 |
Jul 07 08:02:01 PM PDT 24 |
4580453972 ps |
| T401 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1242847582 |
|
|
Jul 07 07:43:55 PM PDT 24 |
Jul 07 07:46:07 PM PDT 24 |
2006474080 ps |
| T751 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2225038492 |
|
|
Jul 07 07:28:17 PM PDT 24 |
Jul 07 07:30:44 PM PDT 24 |
3265735050 ps |
| T1106 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.528909742 |
|
|
Jul 07 07:25:48 PM PDT 24 |
Jul 07 07:36:05 PM PDT 24 |
4330033332 ps |