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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.56 94.40 95.37 95.25 97.53 99.52


Total test records in report: 2908
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T814 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3580107960 Jul 07 07:57:59 PM PDT 24 Jul 07 08:10:34 PM PDT 24 5390018288 ps
T354 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4035704275 Jul 07 07:18:09 PM PDT 24 Jul 07 07:31:51 PM PDT 24 4243820991 ps
T222 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2067025133 Jul 07 07:41:42 PM PDT 24 Jul 07 07:47:42 PM PDT 24 4136599384 ps
T1107 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4040629733 Jul 07 07:29:37 PM PDT 24 Jul 07 08:36:36 PM PDT 24 15026315928 ps
T1108 /workspace/coverage/default/0.chip_tap_straps_rma.3983056146 Jul 07 07:20:46 PM PDT 24 Jul 07 07:24:58 PM PDT 24 3721444852 ps
T1109 /workspace/coverage/default/0.chip_tap_straps_dev.2606357370 Jul 07 07:19:03 PM PDT 24 Jul 07 07:23:44 PM PDT 24 3303467765 ps
T837 /workspace/coverage/default/46.chip_sw_all_escalation_resets.572815600 Jul 07 07:55:54 PM PDT 24 Jul 07 08:06:09 PM PDT 24 6097751088 ps
T812 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1923939929 Jul 07 07:52:15 PM PDT 24 Jul 07 08:00:14 PM PDT 24 3974870590 ps
T1110 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.22172984 Jul 07 07:46:17 PM PDT 24 Jul 07 07:56:40 PM PDT 24 4012124224 ps
T1111 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4201022103 Jul 07 07:39:39 PM PDT 24 Jul 07 08:07:24 PM PDT 24 13358488250 ps
T1112 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3285060026 Jul 07 07:35:09 PM PDT 24 Jul 07 07:39:21 PM PDT 24 3352024469 ps
T197 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4197672463 Jul 07 07:34:50 PM PDT 24 Jul 07 07:38:24 PM PDT 24 2936615424 ps
T1113 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2754077647 Jul 07 07:49:10 PM PDT 24 Jul 07 08:56:40 PM PDT 24 15298458377 ps
T373 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4073092745 Jul 07 07:36:00 PM PDT 24 Jul 07 07:40:49 PM PDT 24 2667349018 ps
T834 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3237111229 Jul 07 07:53:12 PM PDT 24 Jul 07 07:58:11 PM PDT 24 3516331910 ps
T532 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.358191099 Jul 07 07:38:27 PM PDT 24 Jul 07 07:59:55 PM PDT 24 9281075839 ps
T1114 /workspace/coverage/default/2.chip_sw_hmac_enc.485691702 Jul 07 07:42:30 PM PDT 24 Jul 07 07:47:52 PM PDT 24 2876232720 ps
T1115 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2396877567 Jul 07 07:46:14 PM PDT 24 Jul 07 08:06:47 PM PDT 24 7582403947 ps
T1116 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2463678463 Jul 07 07:43:59 PM PDT 24 Jul 07 08:04:52 PM PDT 24 10245178734 ps
T1117 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2887574710 Jul 07 07:44:28 PM PDT 24 Jul 07 07:50:04 PM PDT 24 3004297328 ps
T1118 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.371074929 Jul 07 07:50:02 PM PDT 24 Jul 07 09:08:52 PM PDT 24 20428285798 ps
T367 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3179628214 Jul 07 07:35:01 PM PDT 24 Jul 07 07:46:11 PM PDT 24 4945593950 ps
T253 /workspace/coverage/default/0.chip_sw_flash_init.2468210772 Jul 07 07:18:05 PM PDT 24 Jul 07 07:49:23 PM PDT 24 25030851526 ps
T1119 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4265555159 Jul 07 07:19:45 PM PDT 24 Jul 07 07:51:23 PM PDT 24 11154494795 ps
T1120 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2526733356 Jul 07 07:38:39 PM PDT 24 Jul 07 07:41:59 PM PDT 24 2507050420 ps
T1121 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4112612490 Jul 07 07:43:12 PM PDT 24 Jul 07 07:53:38 PM PDT 24 5122592912 ps
T38 /workspace/coverage/default/0.chip_sw_gpio.1159107802 Jul 07 07:18:19 PM PDT 24 Jul 07 07:27:15 PM PDT 24 4411298742 ps
T839 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1207549941 Jul 07 07:52:07 PM PDT 24 Jul 07 08:00:07 PM PDT 24 3221378788 ps
T1122 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.128967307 Jul 07 07:26:47 PM PDT 24 Jul 07 07:50:09 PM PDT 24 5703023167 ps
T1123 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4168029224 Jul 07 07:44:13 PM PDT 24 Jul 07 07:51:18 PM PDT 24 4481236848 ps
T1124 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870275167 Jul 07 07:53:23 PM PDT 24 Jul 07 08:01:05 PM PDT 24 3970896274 ps
T1125 /workspace/coverage/default/0.chip_sw_example_flash.2698017803 Jul 07 07:16:28 PM PDT 24 Jul 07 07:19:17 PM PDT 24 3198755220 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.553994930 Jul 07 07:22:20 PM PDT 24 Jul 07 07:26:43 PM PDT 24 3019496480 ps
T1126 /workspace/coverage/default/2.chip_sw_aes_entropy.3727351885 Jul 07 07:40:21 PM PDT 24 Jul 07 07:44:34 PM PDT 24 2850462998 ps
T1127 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2406946403 Jul 07 07:19:08 PM PDT 24 Jul 07 07:25:44 PM PDT 24 3535224232 ps
T1128 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2260663397 Jul 07 07:31:00 PM PDT 24 Jul 07 07:56:38 PM PDT 24 5667419140 ps
T883 /workspace/coverage/default/35.chip_sw_all_escalation_resets.140164944 Jul 07 07:53:43 PM PDT 24 Jul 07 08:03:45 PM PDT 24 3893192008 ps
T1129 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2214292907 Jul 07 07:27:59 PM PDT 24 Jul 07 08:41:46 PM PDT 24 15674431370 ps
T254 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.22520262 Jul 07 07:17:24 PM PDT 24 Jul 07 07:24:22 PM PDT 24 4351284220 ps
T844 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1152730120 Jul 07 07:52:14 PM PDT 24 Jul 07 08:04:41 PM PDT 24 5534149876 ps
T299 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1992741638 Jul 07 07:20:21 PM PDT 24 Jul 07 07:29:21 PM PDT 24 4386154384 ps
T884 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2175362013 Jul 07 07:55:53 PM PDT 24 Jul 07 08:08:33 PM PDT 24 4966993324 ps
T802 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.59240901 Jul 07 07:54:32 PM PDT 24 Jul 07 08:01:04 PM PDT 24 3703441600 ps
T1130 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2694534073 Jul 07 07:34:44 PM PDT 24 Jul 07 08:14:29 PM PDT 24 21080111687 ps
T1131 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1425943325 Jul 07 07:19:51 PM PDT 24 Jul 07 07:40:27 PM PDT 24 6525187396 ps
T1132 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1374171412 Jul 07 07:26:48 PM PDT 24 Jul 07 07:31:37 PM PDT 24 3040683410 ps
T1133 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1690171332 Jul 07 07:35:04 PM PDT 24 Jul 07 07:42:41 PM PDT 24 5450469818 ps
T1134 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1774294673 Jul 07 07:19:07 PM PDT 24 Jul 07 07:30:15 PM PDT 24 3698683552 ps
T1135 /workspace/coverage/default/2.chip_sw_otbn_randomness.2201979872 Jul 07 07:39:47 PM PDT 24 Jul 07 07:57:39 PM PDT 24 5836171664 ps
T810 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1261376731 Jul 07 07:58:39 PM PDT 24 Jul 07 08:06:38 PM PDT 24 4208877080 ps
T413 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4273949534 Jul 07 07:43:23 PM PDT 24 Jul 07 07:48:06 PM PDT 24 2793969772 ps
T848 /workspace/coverage/default/94.chip_sw_all_escalation_resets.504245534 Jul 07 07:58:37 PM PDT 24 Jul 07 08:08:33 PM PDT 24 4647690444 ps
T1136 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2089575857 Jul 07 07:53:29 PM PDT 24 Jul 07 09:05:18 PM PDT 24 14751927214 ps
T300 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.633357468 Jul 07 07:35:20 PM PDT 24 Jul 07 07:44:45 PM PDT 24 4377405346 ps
T1137 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1143667610 Jul 07 07:35:35 PM PDT 24 Jul 07 07:40:48 PM PDT 24 2552330101 ps
T782 /workspace/coverage/default/1.chip_sw_power_idle_load.3843614835 Jul 07 07:35:22 PM PDT 24 Jul 07 07:48:11 PM PDT 24 4883032980 ps
T1138 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3606282093 Jul 07 07:40:28 PM PDT 24 Jul 07 08:06:25 PM PDT 24 6083636280 ps
T889 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1075751735 Jul 07 07:56:59 PM PDT 24 Jul 07 08:08:05 PM PDT 24 6144235692 ps
T12 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1606728271 Jul 07 07:38:14 PM PDT 24 Jul 07 07:42:59 PM PDT 24 3806971066 ps
T1139 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.851975210 Jul 07 07:25:36 PM PDT 24 Jul 07 08:44:43 PM PDT 24 15554919788 ps
T1140 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4191650922 Jul 07 07:29:16 PM PDT 24 Jul 07 07:37:29 PM PDT 24 5420254560 ps
T1141 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3251636071 Jul 07 07:36:07 PM PDT 24 Jul 07 07:40:38 PM PDT 24 2932626448 ps
T878 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1726366349 Jul 07 07:50:38 PM PDT 24 Jul 07 07:57:02 PM PDT 24 3674814020 ps
T887 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3575777830 Jul 07 07:50:47 PM PDT 24 Jul 07 07:56:55 PM PDT 24 3584483712 ps
T864 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2870620284 Jul 07 07:56:38 PM PDT 24 Jul 07 08:05:51 PM PDT 24 4275731450 ps
T1142 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1707840706 Jul 07 07:17:49 PM PDT 24 Jul 07 07:27:41 PM PDT 24 7236918615 ps
T865 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3244511042 Jul 07 07:53:35 PM PDT 24 Jul 07 08:07:01 PM PDT 24 4340407240 ps
T1143 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1521753656 Jul 07 07:18:15 PM PDT 24 Jul 07 07:23:47 PM PDT 24 4761827826 ps
T1144 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1558974178 Jul 07 07:41:31 PM PDT 24 Jul 07 07:57:52 PM PDT 24 6988585015 ps
T862 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3889035186 Jul 07 07:52:22 PM PDT 24 Jul 07 08:02:59 PM PDT 24 5504195120 ps
T1145 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3833916942 Jul 07 07:29:22 PM PDT 24 Jul 07 07:45:57 PM PDT 24 9102623544 ps
T9 /workspace/coverage/default/0.chip_jtag_csr_rw.2167772053 Jul 07 07:10:54 PM PDT 24 Jul 07 07:48:32 PM PDT 24 19504603398 ps
T881 /workspace/coverage/default/75.chip_sw_all_escalation_resets.946669507 Jul 07 07:59:19 PM PDT 24 Jul 07 08:12:20 PM PDT 24 5216236500 ps
T1146 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3970588734 Jul 07 07:51:38 PM PDT 24 Jul 07 08:02:24 PM PDT 24 4966949848 ps
T1147 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.954902749 Jul 07 07:26:37 PM PDT 24 Jul 07 08:28:09 PM PDT 24 14373655170 ps
T256 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4051958915 Jul 07 07:23:16 PM PDT 24 Jul 07 07:33:11 PM PDT 24 4977037544 ps
T276 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.395850597 Jul 07 07:50:21 PM PDT 24 Jul 07 08:01:48 PM PDT 24 4942525954 ps
T277 /workspace/coverage/default/3.chip_sw_uart_tx_rx.742271075 Jul 07 07:46:26 PM PDT 24 Jul 07 07:58:37 PM PDT 24 4664734644 ps
T278 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4013139202 Jul 07 07:54:28 PM PDT 24 Jul 07 08:00:58 PM PDT 24 3511727672 ps
T279 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.674876217 Jul 07 07:18:38 PM PDT 24 Jul 07 07:30:26 PM PDT 24 4997523243 ps
T280 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1445088345 Jul 07 07:43:29 PM PDT 24 Jul 07 08:02:23 PM PDT 24 7456638868 ps
T281 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2425525462 Jul 07 07:44:02 PM PDT 24 Jul 07 07:53:29 PM PDT 24 6784542120 ps
T282 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.180230367 Jul 07 07:32:42 PM PDT 24 Jul 07 07:47:30 PM PDT 24 8464404310 ps
T283 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2394939490 Jul 07 07:26:59 PM PDT 24 Jul 07 07:33:02 PM PDT 24 3306927664 ps
T107 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1234887893 Jul 07 07:18:32 PM PDT 24 Jul 07 07:27:25 PM PDT 24 7652011900 ps
T424 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.294515247 Jul 07 07:33:31 PM PDT 24 Jul 07 07:43:33 PM PDT 24 7456530296 ps
T1148 /workspace/coverage/default/0.rom_volatile_raw_unlock.4091891109 Jul 07 07:24:18 PM PDT 24 Jul 07 07:26:09 PM PDT 24 2388336740 ps
T1149 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1206818705 Jul 07 07:44:45 PM PDT 24 Jul 07 08:12:05 PM PDT 24 6267227160 ps
T1150 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.81599855 Jul 07 07:18:21 PM PDT 24 Jul 07 07:21:21 PM PDT 24 2709361952 ps
T1151 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3468578326 Jul 07 07:41:00 PM PDT 24 Jul 07 07:46:08 PM PDT 24 3134437614 ps
T1152 /workspace/coverage/default/0.chip_sw_csrng_kat_test.146534008 Jul 07 07:17:13 PM PDT 24 Jul 07 07:20:22 PM PDT 24 3343231574 ps
T357 /workspace/coverage/default/0.chip_sw_pattgen_ios.1281838806 Jul 07 07:17:17 PM PDT 24 Jul 07 07:21:54 PM PDT 24 3101573900 ps
T1153 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3538148534 Jul 07 07:17:11 PM PDT 24 Jul 07 07:30:56 PM PDT 24 9997300180 ps
T1154 /workspace/coverage/default/1.chip_sw_kmac_smoketest.335350761 Jul 07 07:36:36 PM PDT 24 Jul 07 07:43:01 PM PDT 24 3280831952 ps
T1155 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4013546278 Jul 07 07:32:16 PM PDT 24 Jul 07 07:51:11 PM PDT 24 5818666800 ps
T1156 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1004489119 Jul 07 07:44:29 PM PDT 24 Jul 07 08:04:28 PM PDT 24 5770506880 ps
T1157 /workspace/coverage/default/1.chip_sw_kmac_idle.1554576733 Jul 07 07:31:18 PM PDT 24 Jul 07 07:36:55 PM PDT 24 2809390250 ps
T1158 /workspace/coverage/default/1.chip_tap_straps_dev.843396074 Jul 07 07:33:34 PM PDT 24 Jul 07 07:36:13 PM PDT 24 2755278157 ps
T1159 /workspace/coverage/default/1.rom_e2e_smoke.779206932 Jul 07 07:41:19 PM PDT 24 Jul 07 08:43:00 PM PDT 24 14659128368 ps
T1160 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1982064014 Jul 07 07:47:49 PM PDT 24 Jul 07 09:08:46 PM PDT 24 19762684196 ps
T1161 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1047318227 Jul 07 07:18:34 PM PDT 24 Jul 07 07:34:39 PM PDT 24 7444160048 ps
T854 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3775789660 Jul 07 07:55:54 PM PDT 24 Jul 07 08:10:17 PM PDT 24 5806020882 ps
T1162 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1058414903 Jul 07 07:44:32 PM PDT 24 Jul 07 07:54:20 PM PDT 24 3404292582 ps
T140 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2789794240 Jul 07 07:43:11 PM PDT 24 Jul 07 07:50:54 PM PDT 24 5605006720 ps
T1163 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.518687883 Jul 07 07:16:51 PM PDT 24 Jul 07 07:18:48 PM PDT 24 2740743460 ps
T1164 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1248649040 Jul 07 07:25:57 PM PDT 24 Jul 07 07:49:20 PM PDT 24 9572111820 ps
T1165 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2837191974 Jul 07 07:22:35 PM PDT 24 Jul 07 07:55:57 PM PDT 24 8708341100 ps
T1166 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1597319361 Jul 07 07:39:15 PM PDT 24 Jul 07 07:52:59 PM PDT 24 6615959190 ps
T1167 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4164791314 Jul 07 07:17:14 PM PDT 24 Jul 07 07:21:39 PM PDT 24 2896634596 ps
T1168 /workspace/coverage/default/2.rom_keymgr_functest.2006302853 Jul 07 07:48:23 PM PDT 24 Jul 07 07:59:27 PM PDT 24 5816249280 ps
T855 /workspace/coverage/default/4.chip_sw_all_escalation_resets.1661670327 Jul 07 07:48:35 PM PDT 24 Jul 07 08:01:59 PM PDT 24 6125944192 ps
T382 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1984238860 Jul 07 07:53:15 PM PDT 24 Jul 07 08:02:06 PM PDT 24 4545356680 ps
T257 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2687916703 Jul 07 07:37:44 PM PDT 24 Jul 07 07:48:34 PM PDT 24 6336145972 ps
T368 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1300452784 Jul 07 07:56:54 PM PDT 24 Jul 07 08:07:32 PM PDT 24 5423768012 ps
T1169 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.115719127 Jul 07 07:31:02 PM PDT 24 Jul 07 08:44:25 PM PDT 24 16309830008 ps
T1170 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.389011745 Jul 07 07:27:44 PM PDT 24 Jul 07 07:37:27 PM PDT 24 6959667934 ps
T1171 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.303778063 Jul 07 07:48:29 PM PDT 24 Jul 07 08:31:52 PM PDT 24 12999073000 ps
T775 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2385823331 Jul 07 07:20:41 PM PDT 24 Jul 07 07:52:49 PM PDT 24 21574736664 ps
T811 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504400401 Jul 07 07:54:55 PM PDT 24 Jul 07 08:01:37 PM PDT 24 4326488556 ps
T1172 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.542506988 Jul 07 07:51:20 PM PDT 24 Jul 07 07:58:59 PM PDT 24 5363453833 ps
T1173 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3470104343 Jul 07 07:28:03 PM PDT 24 Jul 07 07:47:31 PM PDT 24 6186779967 ps
T1174 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2295764400 Jul 07 07:18:47 PM PDT 24 Jul 07 07:29:13 PM PDT 24 5451639104 ps
T1175 /workspace/coverage/default/1.chip_sw_example_flash.1772057515 Jul 07 07:24:18 PM PDT 24 Jul 07 07:28:07 PM PDT 24 3337030272 ps
T1176 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4132697710 Jul 07 07:37:24 PM PDT 24 Jul 07 07:46:19 PM PDT 24 4579421600 ps
T1177 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2430690772 Jul 07 07:23:16 PM PDT 24 Jul 07 07:26:56 PM PDT 24 2609924080 ps
T1178 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.604251294 Jul 07 07:22:42 PM PDT 24 Jul 07 08:01:16 PM PDT 24 29995916700 ps
T1179 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3747905914 Jul 07 07:39:57 PM PDT 24 Jul 07 07:46:58 PM PDT 24 4135873008 ps
T803 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.462002170 Jul 07 07:50:30 PM PDT 24 Jul 07 07:57:59 PM PDT 24 4257216856 ps
T1180 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3191746417 Jul 07 07:34:45 PM PDT 24 Jul 07 07:44:57 PM PDT 24 4935734536 ps
T1181 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.808046048 Jul 07 07:30:59 PM PDT 24 Jul 07 07:40:33 PM PDT 24 5186493720 ps
T1182 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3121636161 Jul 07 07:51:11 PM PDT 24 Jul 07 08:10:00 PM PDT 24 12215824286 ps
T1183 /workspace/coverage/default/2.chip_sw_aes_enc.3558935675 Jul 07 07:41:37 PM PDT 24 Jul 07 07:46:27 PM PDT 24 2858856154 ps
T1184 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.370568831 Jul 07 07:45:50 PM PDT 24 Jul 07 07:52:00 PM PDT 24 2934045066 ps
T258 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1813778892 Jul 07 07:28:02 PM PDT 24 Jul 07 07:40:32 PM PDT 24 6570693510 ps
T1185 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4053345500 Jul 07 07:30:44 PM PDT 24 Jul 07 07:52:31 PM PDT 24 5896383504 ps
T1186 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3095813819 Jul 07 07:28:23 PM PDT 24 Jul 07 08:05:20 PM PDT 24 33986163000 ps
T1187 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3323254853 Jul 07 07:28:06 PM PDT 24 Jul 07 07:37:21 PM PDT 24 6717604952 ps
T785 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2158800077 Jul 07 07:25:51 PM PDT 24 Jul 07 08:04:36 PM PDT 24 11827777917 ps
T1188 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3543354517 Jul 07 07:17:37 PM PDT 24 Jul 07 07:22:01 PM PDT 24 2363414744 ps
T321 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1021644045 Jul 07 07:22:59 PM PDT 24 Jul 07 07:33:18 PM PDT 24 6810523322 ps
T866 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3447886311 Jul 07 07:56:12 PM PDT 24 Jul 07 08:07:14 PM PDT 24 4352188984 ps
T223 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.179117667 Jul 07 07:30:55 PM PDT 24 Jul 07 07:36:11 PM PDT 24 2708486310 ps
T1189 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4121299117 Jul 07 07:41:15 PM PDT 24 Jul 07 07:44:13 PM PDT 24 2021467800 ps
T1190 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4033871052 Jul 07 07:33:21 PM PDT 24 Jul 07 08:10:30 PM PDT 24 9112729640 ps
T745 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1392463812 Jul 07 07:35:06 PM PDT 24 Jul 07 07:42:47 PM PDT 24 5768342150 ps
T1191 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3043626855 Jul 07 07:16:53 PM PDT 24 Jul 07 07:20:16 PM PDT 24 2930037738 ps
T835 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1963950583 Jul 07 07:52:29 PM PDT 24 Jul 07 08:03:19 PM PDT 24 5541492856 ps
T144 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.766910646 Jul 07 07:20:38 PM PDT 24 Jul 07 07:37:17 PM PDT 24 8488314464 ps
T1192 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.676908696 Jul 07 07:19:14 PM PDT 24 Jul 07 07:21:30 PM PDT 24 2915508829 ps
T1193 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1263082559 Jul 07 07:44:35 PM PDT 24 Jul 07 07:57:14 PM PDT 24 4939246950 ps
T1194 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3874334332 Jul 07 07:40:11 PM PDT 24 Jul 07 07:49:31 PM PDT 24 7003568850 ps
T1195 /workspace/coverage/default/0.chip_sw_power_sleep_load.3473228823 Jul 07 07:20:55 PM PDT 24 Jul 07 07:34:06 PM PDT 24 10078447864 ps
T1196 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.14942762 Jul 07 07:35:50 PM PDT 24 Jul 07 08:06:37 PM PDT 24 8682766556 ps
T1197 /workspace/coverage/default/2.chip_sival_flash_info_access.1434339108 Jul 07 07:35:41 PM PDT 24 Jul 07 07:40:42 PM PDT 24 3169977474 ps
T833 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.768647419 Jul 07 07:57:16 PM PDT 24 Jul 07 08:05:09 PM PDT 24 3333604212 ps
T1198 /workspace/coverage/default/36.chip_sw_all_escalation_resets.265280506 Jul 07 07:53:08 PM PDT 24 Jul 07 08:07:02 PM PDT 24 6058237482 ps
T1199 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.588972741 Jul 07 07:28:47 PM PDT 24 Jul 07 08:33:17 PM PDT 24 14935036130 ps
T1200 /workspace/coverage/default/1.chip_sw_aes_entropy.3784178097 Jul 07 07:29:43 PM PDT 24 Jul 07 07:34:20 PM PDT 24 3179672480 ps
T371 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1216511947 Jul 07 07:20:22 PM PDT 24 Jul 07 07:31:01 PM PDT 24 5224687897 ps
T1201 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.633679443 Jul 07 07:33:34 PM PDT 24 Jul 07 07:45:42 PM PDT 24 5301585512 ps
T1202 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.4101022399 Jul 07 07:35:47 PM PDT 24 Jul 07 07:43:33 PM PDT 24 5510047320 ps
T1203 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3251039605 Jul 07 07:21:04 PM PDT 24 Jul 07 07:25:35 PM PDT 24 3210033648 ps
T1204 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3012910613 Jul 07 07:18:45 PM PDT 24 Jul 07 08:03:33 PM PDT 24 29247279766 ps
T71 /workspace/coverage/default/3.chip_tap_straps_testunlock0.1375100012 Jul 07 07:47:35 PM PDT 24 Jul 07 07:56:44 PM PDT 24 4912821444 ps
T1205 /workspace/coverage/default/2.chip_sw_example_rom.1139417152 Jul 07 07:40:37 PM PDT 24 Jul 07 07:42:33 PM PDT 24 1926255140 ps
T1206 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3650278198 Jul 07 07:23:04 PM PDT 24 Jul 07 08:31:35 PM PDT 24 29151907627 ps
T1207 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.281939893 Jul 07 07:39:15 PM PDT 24 Jul 07 07:57:07 PM PDT 24 11964384511 ps
T360 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2622280477 Jul 07 07:54:05 PM PDT 24 Jul 07 08:03:02 PM PDT 24 5382702342 ps
T793 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2993014449 Jul 07 07:56:32 PM PDT 24 Jul 07 08:08:30 PM PDT 24 5112625122 ps
T1208 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.364249789 Jul 07 07:49:59 PM PDT 24 Jul 07 08:00:04 PM PDT 24 4577251220 ps
T1209 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1670560480 Jul 07 07:49:43 PM PDT 24 Jul 07 07:58:40 PM PDT 24 4361423992 ps
T1210 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2905097498 Jul 07 07:36:25 PM PDT 24 Jul 07 07:42:10 PM PDT 24 3573198464 ps
T216 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3027630112 Jul 07 07:25:56 PM PDT 24 Jul 07 10:32:53 PM PDT 24 59539628858 ps
T1211 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2582262707 Jul 07 07:33:49 PM PDT 24 Jul 07 07:55:55 PM PDT 24 7812215088 ps
T39 /workspace/coverage/default/2.chip_sw_gpio.1174451027 Jul 07 07:37:38 PM PDT 24 Jul 07 07:47:11 PM PDT 24 4370184440 ps
T1212 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2211530033 Jul 07 07:17:19 PM PDT 24 Jul 07 07:26:56 PM PDT 24 4592348030 ps
T820 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.861780642 Jul 07 07:53:27 PM PDT 24 Jul 07 08:00:28 PM PDT 24 3367846768 ps
T1213 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.871061686 Jul 07 07:17:29 PM PDT 24 Jul 07 08:50:57 PM PDT 24 48837974200 ps
T1214 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1921589009 Jul 07 07:37:08 PM PDT 24 Jul 07 08:11:54 PM PDT 24 13571861214 ps
T801 /workspace/coverage/default/0.chip_sw_all_escalation_resets.105276693 Jul 07 07:18:51 PM PDT 24 Jul 07 07:31:20 PM PDT 24 4909512486 ps
T1215 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2061735041 Jul 07 07:46:47 PM PDT 24 Jul 07 07:50:59 PM PDT 24 2655589132 ps
T1216 /workspace/coverage/default/0.chip_sw_otbn_randomness.817957085 Jul 07 07:17:58 PM PDT 24 Jul 07 07:34:16 PM PDT 24 6193986280 ps
T1217 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1922015981 Jul 07 07:31:19 PM PDT 24 Jul 07 08:00:30 PM PDT 24 7793339944 ps
T836 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2309118715 Jul 07 07:58:22 PM PDT 24 Jul 07 08:10:15 PM PDT 24 5218260582 ps
T1218 /workspace/coverage/default/2.chip_sw_example_manufacturer.2560560733 Jul 07 07:43:19 PM PDT 24 Jul 07 07:46:24 PM PDT 24 3104334600 ps
T1219 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2001539633 Jul 07 07:19:54 PM PDT 24 Jul 07 07:27:54 PM PDT 24 4793167887 ps
T1220 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3068958721 Jul 07 07:17:34 PM PDT 24 Jul 07 07:20:45 PM PDT 24 2962652858 ps
T871 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.736545826 Jul 07 07:55:58 PM PDT 24 Jul 07 08:01:53 PM PDT 24 3680961300 ps
T1221 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3326133311 Jul 07 07:18:59 PM PDT 24 Jul 07 07:37:23 PM PDT 24 13493818698 ps
T312 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1157749393 Jul 07 07:34:53 PM PDT 24 Jul 07 07:39:06 PM PDT 24 2744449764 ps
T737 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2243856699 Jul 07 07:41:44 PM PDT 24 Jul 07 07:52:53 PM PDT 24 3640389078 ps
T1222 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2582279613 Jul 07 07:33:03 PM PDT 24 Jul 07 07:38:03 PM PDT 24 2233251640 ps
T374 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3063335731 Jul 07 07:19:24 PM PDT 24 Jul 07 07:23:06 PM PDT 24 2607703104 ps
T1223 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2303564564 Jul 07 07:50:14 PM PDT 24 Jul 07 08:55:28 PM PDT 24 15679431337 ps
T1224 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3599140757 Jul 07 07:58:20 PM PDT 24 Jul 07 08:08:39 PM PDT 24 4666398600 ps
T275 /workspace/coverage/default/98.chip_sw_all_escalation_resets.576431398 Jul 07 07:58:03 PM PDT 24 Jul 07 08:08:09 PM PDT 24 5046756000 ps
T1225 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1473585227 Jul 07 07:49:57 PM PDT 24 Jul 07 08:08:21 PM PDT 24 9644923316 ps
T791 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482514308 Jul 07 07:52:23 PM PDT 24 Jul 07 07:59:16 PM PDT 24 3994456732 ps
T877 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1401156871 Jul 07 07:56:29 PM PDT 24 Jul 07 08:04:00 PM PDT 24 4510559568 ps
T349 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2539392738 Jul 07 07:27:10 PM PDT 24 Jul 07 07:37:51 PM PDT 24 4683997014 ps
T817 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692149602 Jul 07 07:58:21 PM PDT 24 Jul 07 08:06:18 PM PDT 24 3796781890 ps
T1226 /workspace/coverage/default/32.chip_sw_all_escalation_resets.907626786 Jul 07 07:52:43 PM PDT 24 Jul 07 08:05:54 PM PDT 24 4269942720 ps
T1227 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4126189321 Jul 07 07:29:42 PM PDT 24 Jul 07 08:25:04 PM PDT 24 11519677256 ps
T212 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1545094247 Jul 07 07:26:06 PM PDT 24 Jul 07 07:37:26 PM PDT 24 6486755506 ps
T1228 /workspace/coverage/default/0.chip_tap_straps_prod.1142693250 Jul 07 07:19:48 PM PDT 24 Jul 07 07:22:08 PM PDT 24 2208535155 ps
T10 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3332365568 Jul 07 07:20:43 PM PDT 24 Jul 07 07:25:29 PM PDT 24 3384069960 ps
T1229 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4001139805 Jul 07 07:53:23 PM PDT 24 Jul 07 08:00:20 PM PDT 24 4303558072 ps
T825 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1126302391 Jul 07 07:56:22 PM PDT 24 Jul 07 08:07:11 PM PDT 24 5268717390 ps
T1230 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3537314686 Jul 07 07:36:12 PM PDT 24 Jul 07 07:47:37 PM PDT 24 3505509800 ps
T1231 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3885126217 Jul 07 07:17:38 PM PDT 24 Jul 07 07:24:50 PM PDT 24 4771653010 ps
T1232 /workspace/coverage/default/0.chip_sw_flash_crash_alert.3383242365 Jul 07 07:19:45 PM PDT 24 Jul 07 07:33:49 PM PDT 24 5504178380 ps
T1233 /workspace/coverage/default/1.chip_sw_hmac_oneshot.906036170 Jul 07 07:31:40 PM PDT 24 Jul 07 07:36:50 PM PDT 24 2921327800 ps
T1234 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2419073633 Jul 07 07:29:53 PM PDT 24 Jul 07 08:31:25 PM PDT 24 18397716788 ps
T1235 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1512823252 Jul 07 07:32:02 PM PDT 24 Jul 07 07:40:22 PM PDT 24 5098152340 ps
T831 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3750506645 Jul 07 07:52:28 PM PDT 24 Jul 07 08:02:56 PM PDT 24 5482709450 ps
T1236 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1824872026 Jul 07 07:24:15 PM PDT 24 Jul 07 07:28:20 PM PDT 24 3490519004 ps
T776 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2788763980 Jul 07 07:45:43 PM PDT 24 Jul 07 08:10:00 PM PDT 24 24465440456 ps
T879 /workspace/coverage/default/45.chip_sw_all_escalation_resets.1914504579 Jul 07 07:54:49 PM PDT 24 Jul 07 08:08:15 PM PDT 24 5183809608 ps
T1237 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1350197371 Jul 07 07:36:18 PM PDT 24 Jul 07 07:44:05 PM PDT 24 3368330624 ps
T1238 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1857757996 Jul 07 07:20:47 PM PDT 24 Jul 07 07:24:03 PM PDT 24 2924896817 ps
T1239 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2609985233 Jul 07 07:50:12 PM PDT 24 Jul 07 07:58:31 PM PDT 24 6835194437 ps
T1240 /workspace/coverage/default/0.rom_keymgr_functest.3320553259 Jul 07 07:23:49 PM PDT 24 Jul 07 07:32:05 PM PDT 24 3745479264 ps
T1241 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1401267387 Jul 07 07:31:17 PM PDT 24 Jul 07 07:53:48 PM PDT 24 7354356720 ps
T1242 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2243300695 Jul 07 07:28:05 PM PDT 24 Jul 07 07:39:08 PM PDT 24 4680349024 ps
T1243 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2351137491 Jul 07 07:46:07 PM PDT 24 Jul 07 07:51:39 PM PDT 24 2471001328 ps
T1244 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3261856302 Jul 07 07:32:35 PM PDT 24 Jul 07 08:12:22 PM PDT 24 25173780900 ps
T1245 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1478195009 Jul 07 07:50:03 PM PDT 24 Jul 07 08:48:36 PM PDT 24 15420292369 ps
T399 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2036941398 Jul 07 07:25:49 PM PDT 24 Jul 07 09:08:33 PM PDT 24 23055570184 ps
T828 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1062820438 Jul 07 07:55:13 PM PDT 24 Jul 07 08:01:02 PM PDT 24 3806436264 ps
T858 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3569311721 Jul 07 07:55:12 PM PDT 24 Jul 07 08:09:14 PM PDT 24 6506495634 ps
T1246 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4190733004 Jul 07 07:35:12 PM PDT 24 Jul 07 08:06:11 PM PDT 24 10541157079 ps
T1247 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3964873454 Jul 07 07:47:24 PM PDT 24 Jul 07 07:55:58 PM PDT 24 3664883217 ps
T313 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1679422403 Jul 07 07:20:43 PM PDT 24 Jul 07 07:25:41 PM PDT 24 2544816770 ps
T362 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2695078725 Jul 07 07:44:57 PM PDT 24 Jul 07 08:00:06 PM PDT 24 5068891538 ps
T1248 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1580792623 Jul 07 07:19:50 PM PDT 24 Jul 07 09:06:40 PM PDT 24 26029865550 ps
T46 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2108716099 Jul 07 07:37:44 PM PDT 24 Jul 07 07:41:20 PM PDT 24 2378204822 ps
T1249 /workspace/coverage/default/2.chip_sw_aes_idle.720676136 Jul 07 07:42:13 PM PDT 24 Jul 07 07:47:24 PM PDT 24 2861005380 ps
T1250 /workspace/coverage/default/0.chip_sw_kmac_entropy.924597982 Jul 07 07:22:03 PM PDT 24 Jul 07 07:27:08 PM PDT 24 2378144072 ps
T1251 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1544460082 Jul 07 07:33:11 PM PDT 24 Jul 07 07:43:43 PM PDT 24 3890134798 ps
T175 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3964239809 Jul 07 07:39:15 PM PDT 24 Jul 07 07:41:17 PM PDT 24 2312896884 ps
T826 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756953915 Jul 07 07:49:29 PM PDT 24 Jul 07 07:58:40 PM PDT 24 4497621640 ps
T830 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3596490510 Jul 07 07:58:22 PM PDT 24 Jul 07 08:11:18 PM PDT 24 6310809248 ps
T1252 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1500362072 Jul 07 07:56:40 PM PDT 24 Jul 07 08:05:08 PM PDT 24 4077693940 ps
T1253 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3108437829 Jul 07 07:40:31 PM PDT 24 Jul 07 07:44:05 PM PDT 24 2147004128 ps
T869 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2856536933 Jul 07 07:57:18 PM PDT 24 Jul 07 08:03:46 PM PDT 24 3991647960 ps
T269 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.805798423 Jul 07 07:21:54 PM PDT 24 Jul 07 08:01:32 PM PDT 24 11770628820 ps
T1254 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1811539683 Jul 07 07:19:25 PM PDT 24 Jul 07 07:28:32 PM PDT 24 5624725528 ps
T141 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.757946260 Jul 07 07:31:49 PM PDT 24 Jul 07 07:41:26 PM PDT 24 5830980432 ps
T1255 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4138624445 Jul 07 07:36:22 PM PDT 24 Jul 07 07:45:11 PM PDT 24 3411469158 ps
T202 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3606295640 Jul 07 07:33:31 PM PDT 24 Jul 07 07:41:15 PM PDT 24 4185712118 ps
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