| T1256 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2824539158 |
|
|
Jul 07 07:26:00 PM PDT 24 |
Jul 07 07:30:22 PM PDT 24 |
2828236096 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.3901470471 |
|
|
Jul 07 07:44:02 PM PDT 24 |
Jul 07 08:16:36 PM PDT 24 |
7840084544 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.400596415 |
|
|
Jul 07 07:46:47 PM PDT 24 |
Jul 07 07:51:41 PM PDT 24 |
2501085640 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3523655207 |
|
|
Jul 07 07:44:07 PM PDT 24 |
Jul 07 08:03:45 PM PDT 24 |
5804271816 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2477086906 |
|
|
Jul 07 07:46:26 PM PDT 24 |
Jul 07 07:51:44 PM PDT 24 |
2887743384 ps |
| T882 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3061501985 |
|
|
Jul 07 07:49:22 PM PDT 24 |
Jul 07 07:57:24 PM PDT 24 |
3354557542 ps |
| T169 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1139165308 |
|
|
Jul 07 07:18:31 PM PDT 24 |
Jul 07 07:28:17 PM PDT 24 |
4241596460 ps |
| T1261 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3843555775 |
|
|
Jul 07 07:29:05 PM PDT 24 |
Jul 07 07:37:10 PM PDT 24 |
3672068270 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2803666458 |
|
|
Jul 07 07:22:38 PM PDT 24 |
Jul 07 07:28:21 PM PDT 24 |
3660571362 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3380384508 |
|
|
Jul 07 07:18:26 PM PDT 24 |
Jul 07 07:32:58 PM PDT 24 |
5456750522 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3361769547 |
|
|
Jul 07 07:26:11 PM PDT 24 |
Jul 07 07:30:03 PM PDT 24 |
2859108752 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3768461769 |
|
|
Jul 07 07:19:49 PM PDT 24 |
Jul 07 07:26:30 PM PDT 24 |
6381690744 ps |
| T145 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2845975500 |
|
|
Jul 07 07:49:58 PM PDT 24 |
Jul 07 08:09:05 PM PDT 24 |
9955326136 ps |
| T47 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2002272422 |
|
|
Jul 07 07:18:03 PM PDT 24 |
Jul 07 07:22:22 PM PDT 24 |
3465447860 ps |
| T1264 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4209805700 |
|
|
Jul 07 07:55:10 PM PDT 24 |
Jul 07 08:01:58 PM PDT 24 |
3295598260 ps |
| T1265 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4019234656 |
|
|
Jul 07 07:25:31 PM PDT 24 |
Jul 07 08:36:57 PM PDT 24 |
15517471680 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3185233359 |
|
|
Jul 07 07:28:10 PM PDT 24 |
Jul 07 07:56:28 PM PDT 24 |
8751341358 ps |
| T1267 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2561534112 |
|
|
Jul 07 07:40:04 PM PDT 24 |
Jul 07 07:45:11 PM PDT 24 |
3393162774 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2671893592 |
|
|
Jul 07 07:44:17 PM PDT 24 |
Jul 07 07:49:46 PM PDT 24 |
2859948711 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3081198045 |
|
|
Jul 07 07:44:06 PM PDT 24 |
Jul 07 07:54:49 PM PDT 24 |
7129742454 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1788772128 |
|
|
Jul 07 07:40:46 PM PDT 24 |
Jul 07 07:43:45 PM PDT 24 |
2651147432 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1417028094 |
|
|
Jul 07 07:45:46 PM PDT 24 |
Jul 07 07:51:48 PM PDT 24 |
2606601032 ps |
| T821 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515973072 |
|
|
Jul 07 07:51:22 PM PDT 24 |
Jul 07 07:59:09 PM PDT 24 |
3530463840 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.776239521 |
|
|
Jul 07 07:17:41 PM PDT 24 |
Jul 07 07:27:09 PM PDT 24 |
4391402016 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2506311450 |
|
|
Jul 07 07:23:53 PM PDT 24 |
Jul 07 07:28:41 PM PDT 24 |
2990897128 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1435241761 |
|
|
Jul 07 07:31:15 PM PDT 24 |
Jul 07 07:36:19 PM PDT 24 |
2159388800 ps |
| T20 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3292167888 |
|
|
Jul 07 07:35:52 PM PDT 24 |
Jul 07 07:39:55 PM PDT 24 |
3289522356 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3514858302 |
|
|
Jul 07 07:46:28 PM PDT 24 |
Jul 07 07:59:16 PM PDT 24 |
4598438430 ps |
| T850 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3361299618 |
|
|
Jul 07 07:51:31 PM PDT 24 |
Jul 07 08:01:17 PM PDT 24 |
4758939884 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.4154693460 |
|
|
Jul 07 07:37:56 PM PDT 24 |
Jul 07 10:48:21 PM PDT 24 |
64314955712 ps |
| T213 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.255487809 |
|
|
Jul 07 07:37:44 PM PDT 24 |
Jul 07 07:55:51 PM PDT 24 |
8662192436 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1986408815 |
|
|
Jul 07 07:45:25 PM PDT 24 |
Jul 07 07:56:43 PM PDT 24 |
5732091659 ps |
| T1276 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3121977393 |
|
|
Jul 07 07:23:47 PM PDT 24 |
Jul 07 07:45:24 PM PDT 24 |
8211476792 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3794248509 |
|
|
Jul 07 07:24:13 PM PDT 24 |
Jul 07 07:28:33 PM PDT 24 |
3283605069 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2573247545 |
|
|
Jul 07 07:17:35 PM PDT 24 |
Jul 07 08:26:33 PM PDT 24 |
19559253987 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.466567878 |
|
|
Jul 07 07:18:03 PM PDT 24 |
Jul 07 07:26:38 PM PDT 24 |
5465143950 ps |
| T838 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.138015271 |
|
|
Jul 07 07:55:09 PM PDT 24 |
Jul 07 08:06:55 PM PDT 24 |
4246881230 ps |
| T1280 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.4245772296 |
|
|
Jul 07 07:39:47 PM PDT 24 |
Jul 07 07:48:09 PM PDT 24 |
3933596584 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.61590454 |
|
|
Jul 07 07:43:19 PM PDT 24 |
Jul 07 07:58:00 PM PDT 24 |
4467838040 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2897062453 |
|
|
Jul 07 07:29:57 PM PDT 24 |
Jul 07 07:53:37 PM PDT 24 |
7424839560 ps |
| T1283 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635688499 |
|
|
Jul 07 07:57:52 PM PDT 24 |
Jul 07 08:05:10 PM PDT 24 |
3999143096 ps |
| T798 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2711505690 |
|
|
Jul 07 07:54:28 PM PDT 24 |
Jul 07 08:07:07 PM PDT 24 |
5847556500 ps |
| T856 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2309349753 |
|
|
Jul 07 07:55:19 PM PDT 24 |
Jul 07 08:01:58 PM PDT 24 |
3568290986 ps |
| T1284 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2776676461 |
|
|
Jul 07 07:56:00 PM PDT 24 |
Jul 07 08:08:59 PM PDT 24 |
4770623998 ps |
| T885 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294043231 |
|
|
Jul 07 07:56:57 PM PDT 24 |
Jul 07 08:02:05 PM PDT 24 |
3055664960 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.245794439 |
|
|
Jul 07 07:20:52 PM PDT 24 |
Jul 07 07:43:04 PM PDT 24 |
6316030760 ps |
| T400 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4043158403 |
|
|
Jul 07 07:26:00 PM PDT 24 |
Jul 07 09:28:34 PM PDT 24 |
24640334032 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.224585560 |
|
|
Jul 07 07:37:47 PM PDT 24 |
Jul 07 07:44:31 PM PDT 24 |
2481072242 ps |
| T1287 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4204318110 |
|
|
Jul 07 07:29:09 PM PDT 24 |
Jul 07 08:34:21 PM PDT 24 |
14501635496 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3720455713 |
|
|
Jul 07 07:17:07 PM PDT 24 |
Jul 07 07:21:43 PM PDT 24 |
2974739492 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2799426969 |
|
|
Jul 07 07:23:00 PM PDT 24 |
Jul 07 07:26:30 PM PDT 24 |
2939724557 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2975323136 |
|
|
Jul 07 07:18:13 PM PDT 24 |
Jul 07 07:37:15 PM PDT 24 |
8904722520 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1750409820 |
|
|
Jul 07 07:19:43 PM PDT 24 |
Jul 07 07:27:02 PM PDT 24 |
3209074532 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.820247697 |
|
|
Jul 07 07:17:16 PM PDT 24 |
Jul 07 07:44:33 PM PDT 24 |
23651520616 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2045990166 |
|
|
Jul 07 07:20:52 PM PDT 24 |
Jul 07 08:13:31 PM PDT 24 |
13229316509 ps |
| T334 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.581527952 |
|
|
Jul 07 07:32:26 PM PDT 24 |
Jul 07 07:46:43 PM PDT 24 |
5209235000 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.65376674 |
|
|
Jul 07 07:22:21 PM PDT 24 |
Jul 07 07:27:08 PM PDT 24 |
2699946872 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1838307688 |
|
|
Jul 07 07:37:48 PM PDT 24 |
Jul 07 07:49:12 PM PDT 24 |
4145466524 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.790479917 |
|
|
Jul 07 07:41:28 PM PDT 24 |
Jul 07 07:51:00 PM PDT 24 |
8116917298 ps |
| T1294 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.40535498 |
|
|
Jul 07 08:00:02 PM PDT 24 |
Jul 07 08:06:55 PM PDT 24 |
3983265680 ps |
| T146 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2801866281 |
|
|
Jul 07 07:31:57 PM PDT 24 |
Jul 07 07:46:59 PM PDT 24 |
8330242856 ps |
| T1295 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3699734219 |
|
|
Jul 07 07:28:12 PM PDT 24 |
Jul 07 08:38:07 PM PDT 24 |
15143252990 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.53655193 |
|
|
Jul 07 07:19:23 PM PDT 24 |
Jul 07 07:39:42 PM PDT 24 |
6781974648 ps |
| T1297 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1849728113 |
|
|
Jul 07 07:51:54 PM PDT 24 |
Jul 07 08:17:00 PM PDT 24 |
8154000650 ps |
| T240 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3167113519 |
|
|
Jul 07 07:41:46 PM PDT 24 |
Jul 07 08:28:06 PM PDT 24 |
11316999508 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.874278697 |
|
|
Jul 07 07:38:47 PM PDT 24 |
Jul 07 08:10:31 PM PDT 24 |
8621899785 ps |
| T363 |
/workspace/coverage/default/1.chip_sival_flash_info_access.831643583 |
|
|
Jul 07 07:24:04 PM PDT 24 |
Jul 07 07:28:56 PM PDT 24 |
2550157090 ps |
| T1299 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1527734570 |
|
|
Jul 07 07:48:06 PM PDT 24 |
Jul 07 07:59:31 PM PDT 24 |
4553644010 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.183917166 |
|
|
Jul 07 07:23:34 PM PDT 24 |
Jul 07 07:27:07 PM PDT 24 |
2701801414 ps |
| T1301 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3479696728 |
|
|
Jul 07 07:27:03 PM PDT 24 |
Jul 07 07:47:41 PM PDT 24 |
11591988120 ps |
| T1302 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3835397869 |
|
|
Jul 07 07:43:26 PM PDT 24 |
Jul 07 07:51:55 PM PDT 24 |
5698537800 ps |
| T1303 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2075168311 |
|
|
Jul 07 07:31:17 PM PDT 24 |
Jul 07 07:36:00 PM PDT 24 |
3309009382 ps |
| T1304 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2961668879 |
|
|
Jul 07 07:33:17 PM PDT 24 |
Jul 07 07:43:58 PM PDT 24 |
4993167744 ps |
| T1305 |
/workspace/coverage/default/0.rom_e2e_smoke.130804656 |
|
|
Jul 07 07:26:14 PM PDT 24 |
Jul 07 08:36:12 PM PDT 24 |
15390858420 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3974312283 |
|
|
Jul 07 07:23:25 PM PDT 24 |
Jul 07 07:29:46 PM PDT 24 |
3240996204 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.490909318 |
|
|
Jul 07 07:37:22 PM PDT 24 |
Jul 07 08:06:55 PM PDT 24 |
9255254440 ps |
| T1307 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2610563707 |
|
|
Jul 07 07:58:35 PM PDT 24 |
Jul 07 08:10:40 PM PDT 24 |
4587907212 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4259220448 |
|
|
Jul 07 07:43:12 PM PDT 24 |
Jul 07 07:55:35 PM PDT 24 |
5433429300 ps |
| T170 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1983924101 |
|
|
Jul 07 07:42:44 PM PDT 24 |
Jul 07 07:54:03 PM PDT 24 |
4149762558 ps |
| T1308 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1974956891 |
|
|
Jul 07 07:50:54 PM PDT 24 |
Jul 07 08:05:30 PM PDT 24 |
5620850104 ps |
| T1309 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3203532304 |
|
|
Jul 07 07:25:03 PM PDT 24 |
Jul 07 08:35:51 PM PDT 24 |
13774686502 ps |
| T1310 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2383444007 |
|
|
Jul 07 07:50:35 PM PDT 24 |
Jul 07 08:02:01 PM PDT 24 |
4118945000 ps |
| T1311 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1781479838 |
|
|
Jul 07 07:26:14 PM PDT 24 |
Jul 07 07:34:05 PM PDT 24 |
4670734760 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.952691863 |
|
|
Jul 07 07:19:17 PM PDT 24 |
Jul 07 07:28:50 PM PDT 24 |
5583785580 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2913630533 |
|
|
Jul 07 07:40:29 PM PDT 24 |
Jul 07 08:04:36 PM PDT 24 |
12733502200 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3473534379 |
|
|
Jul 07 07:17:03 PM PDT 24 |
Jul 07 07:27:36 PM PDT 24 |
4210745626 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3493408996 |
|
|
Jul 07 07:24:19 PM PDT 24 |
Jul 07 07:36:00 PM PDT 24 |
4248925638 ps |
| T1316 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.722890121 |
|
|
Jul 07 07:26:43 PM PDT 24 |
Jul 07 09:14:51 PM PDT 24 |
24269078632 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2703454217 |
|
|
Jul 07 07:31:45 PM PDT 24 |
Jul 07 07:36:13 PM PDT 24 |
3013981284 ps |
| T849 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1027853042 |
|
|
Jul 07 07:57:55 PM PDT 24 |
Jul 07 08:09:51 PM PDT 24 |
4447301268 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3401568076 |
|
|
Jul 07 07:24:17 PM PDT 24 |
Jul 07 07:27:27 PM PDT 24 |
2843334996 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1325643133 |
|
|
Jul 07 07:23:16 PM PDT 24 |
Jul 07 07:28:20 PM PDT 24 |
3568660608 ps |
| T425 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2645643416 |
|
|
Jul 07 07:43:26 PM PDT 24 |
Jul 07 07:48:38 PM PDT 24 |
4617583088 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1157497457 |
|
|
Jul 07 07:27:31 PM PDT 24 |
Jul 07 07:29:20 PM PDT 24 |
2332376651 ps |
| T1320 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1919570278 |
|
|
Jul 07 07:53:36 PM PDT 24 |
Jul 07 08:02:40 PM PDT 24 |
4847217380 ps |
| T1321 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.307745104 |
|
|
Jul 07 07:51:57 PM PDT 24 |
Jul 07 09:02:53 PM PDT 24 |
14512021660 ps |
| T1322 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.254453937 |
|
|
Jul 07 07:45:05 PM PDT 24 |
Jul 07 07:52:19 PM PDT 24 |
3588456646 ps |
| T1323 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3799626300 |
|
|
Jul 07 07:43:11 PM PDT 24 |
Jul 07 07:57:38 PM PDT 24 |
4219254152 ps |
| T847 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1020113384 |
|
|
Jul 07 08:00:20 PM PDT 24 |
Jul 07 08:12:08 PM PDT 24 |
5718303326 ps |
| T1324 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3578876741 |
|
|
Jul 07 07:19:54 PM PDT 24 |
Jul 07 07:32:17 PM PDT 24 |
4493172672 ps |
| T1325 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544554773 |
|
|
Jul 07 07:53:06 PM PDT 24 |
Jul 07 07:59:46 PM PDT 24 |
3957022864 ps |
| T531 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.954823588 |
|
|
Jul 07 07:32:12 PM PDT 24 |
Jul 07 07:47:37 PM PDT 24 |
5392727840 ps |
| T1326 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2815726556 |
|
|
Jul 07 07:51:59 PM PDT 24 |
Jul 07 08:43:10 PM PDT 24 |
12705151060 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1555304357 |
|
|
Jul 07 07:18:49 PM PDT 24 |
Jul 07 07:23:06 PM PDT 24 |
2807877166 ps |
| T1328 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1640570116 |
|
|
Jul 07 07:31:28 PM PDT 24 |
Jul 07 07:42:05 PM PDT 24 |
8437104796 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3905636128 |
|
|
Jul 07 07:39:40 PM PDT 24 |
Jul 07 07:47:24 PM PDT 24 |
5846742941 ps |
| T783 |
/workspace/coverage/default/1.rom_raw_unlock.2226670616 |
|
|
Jul 07 07:35:47 PM PDT 24 |
Jul 07 07:39:53 PM PDT 24 |
4474371791 ps |
| T203 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.71549957 |
|
|
Jul 07 07:19:23 PM PDT 24 |
Jul 07 07:28:11 PM PDT 24 |
4991350468 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_edn_kat.3706304829 |
|
|
Jul 07 07:41:45 PM PDT 24 |
Jul 07 07:55:22 PM PDT 24 |
3641861250 ps |
| T1331 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1386015615 |
|
|
Jul 07 07:58:28 PM PDT 24 |
Jul 07 08:07:26 PM PDT 24 |
5553808120 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.3268680125 |
|
|
Jul 07 07:40:22 PM PDT 24 |
Jul 07 07:47:30 PM PDT 24 |
3250366592 ps |
| T1333 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.561135057 |
|
|
Jul 07 07:45:17 PM PDT 24 |
Jul 07 07:49:33 PM PDT 24 |
2925039413 ps |
| T1334 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3507336557 |
|
|
Jul 07 07:49:51 PM PDT 24 |
Jul 07 08:00:25 PM PDT 24 |
5264449480 ps |
| T1335 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1634958310 |
|
|
Jul 07 08:00:39 PM PDT 24 |
Jul 07 08:10:35 PM PDT 24 |
4435922516 ps |
| T152 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4066718228 |
|
|
Jul 07 07:47:30 PM PDT 24 |
Jul 07 08:23:34 PM PDT 24 |
14451455053 ps |
| T1336 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1807191887 |
|
|
Jul 07 07:19:22 PM PDT 24 |
Jul 07 07:39:53 PM PDT 24 |
6139414809 ps |
| T786 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.3419680646 |
|
|
Jul 07 07:24:37 PM PDT 24 |
Jul 07 07:28:39 PM PDT 24 |
2270348170 ps |
| T1337 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3402081729 |
|
|
Jul 07 07:44:38 PM PDT 24 |
Jul 07 07:53:26 PM PDT 24 |
6962621400 ps |
| T863 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3879510723 |
|
|
Jul 07 07:58:03 PM PDT 24 |
Jul 07 08:09:04 PM PDT 24 |
5621452960 ps |
| T1338 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.385715893 |
|
|
Jul 07 07:26:50 PM PDT 24 |
Jul 07 07:33:42 PM PDT 24 |
4018440752 ps |
| T840 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964416725 |
|
|
Jul 07 07:53:20 PM PDT 24 |
Jul 07 08:00:20 PM PDT 24 |
3855398192 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1645029157 |
|
|
Jul 07 07:27:54 PM PDT 24 |
Jul 07 07:47:43 PM PDT 24 |
7037093772 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.884519769 |
|
|
Jul 07 07:36:59 PM PDT 24 |
Jul 07 07:48:12 PM PDT 24 |
4433268820 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2546250610 |
|
|
Jul 07 07:28:40 PM PDT 24 |
Jul 07 07:50:43 PM PDT 24 |
10535675544 ps |
| T1341 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3508216427 |
|
|
Jul 07 07:44:20 PM PDT 24 |
Jul 07 08:23:44 PM PDT 24 |
10939484528 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1190261766 |
|
|
Jul 07 07:18:24 PM PDT 24 |
Jul 07 07:24:31 PM PDT 24 |
3790400989 ps |
| T1342 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3617321572 |
|
|
Jul 07 07:46:58 PM PDT 24 |
Jul 07 07:56:20 PM PDT 24 |
5156860156 ps |
| T1343 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2959884321 |
|
|
Jul 07 07:23:21 PM PDT 24 |
Jul 07 07:42:46 PM PDT 24 |
10491130776 ps |
| T1344 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3667153980 |
|
|
Jul 07 07:53:16 PM PDT 24 |
Jul 07 08:00:45 PM PDT 24 |
4277527990 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2806941849 |
|
|
Jul 07 07:30:37 PM PDT 24 |
Jul 07 07:34:37 PM PDT 24 |
2080351560 ps |
| T1346 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.937459997 |
|
|
Jul 07 07:46:09 PM PDT 24 |
Jul 07 07:49:42 PM PDT 24 |
2686791996 ps |
| T861 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423752944 |
|
|
Jul 07 07:58:25 PM PDT 24 |
Jul 07 08:04:09 PM PDT 24 |
3217597650 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1342758271 |
|
|
Jul 07 07:43:55 PM PDT 24 |
Jul 07 07:55:33 PM PDT 24 |
3766966856 ps |
| T805 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4176278651 |
|
|
Jul 07 07:54:16 PM PDT 24 |
Jul 07 08:05:45 PM PDT 24 |
4817430324 ps |
| T1348 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.4123886252 |
|
|
Jul 07 07:56:07 PM PDT 24 |
Jul 07 08:07:45 PM PDT 24 |
5531013480 ps |
| T1349 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3096289160 |
|
|
Jul 07 07:24:39 PM PDT 24 |
Jul 07 07:29:47 PM PDT 24 |
3066611138 ps |
| T1350 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1389314479 |
|
|
Jul 07 07:40:05 PM PDT 24 |
Jul 07 08:30:31 PM PDT 24 |
11769954030 ps |
| T1351 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.274679944 |
|
|
Jul 07 07:39:11 PM PDT 24 |
Jul 07 07:54:04 PM PDT 24 |
8628292512 ps |
| T818 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4070867120 |
|
|
Jul 07 07:47:50 PM PDT 24 |
Jul 07 07:55:28 PM PDT 24 |
3841174790 ps |
| T1352 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1418107929 |
|
|
Jul 07 07:19:34 PM PDT 24 |
Jul 07 07:54:10 PM PDT 24 |
12298608679 ps |
| T1353 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2226265059 |
|
|
Jul 07 07:27:38 PM PDT 24 |
Jul 07 09:11:02 PM PDT 24 |
24170415574 ps |
| T842 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1206393598 |
|
|
Jul 07 07:18:43 PM PDT 24 |
Jul 07 07:26:20 PM PDT 24 |
4451511160 ps |
| T1354 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2480928400 |
|
|
Jul 07 07:18:46 PM PDT 24 |
Jul 07 07:38:53 PM PDT 24 |
7071145160 ps |
| T788 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.877939340 |
|
|
Jul 07 07:23:39 PM PDT 24 |
Jul 07 08:05:40 PM PDT 24 |
11643268078 ps |
| T875 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.263640982 |
|
|
Jul 07 07:55:32 PM PDT 24 |
Jul 07 08:03:54 PM PDT 24 |
3768075160 ps |
| T1355 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1794002351 |
|
|
Jul 07 07:18:06 PM PDT 24 |
Jul 07 07:29:05 PM PDT 24 |
4359655142 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.1708874352 |
|
|
Jul 07 07:41:46 PM PDT 24 |
Jul 07 07:47:09 PM PDT 24 |
2557523080 ps |
| T1357 |
/workspace/coverage/default/1.chip_sw_aes_enc.489417828 |
|
|
Jul 07 07:29:56 PM PDT 24 |
Jul 07 07:34:26 PM PDT 24 |
2760568298 ps |
| T822 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2297670165 |
|
|
Jul 07 07:30:53 PM PDT 24 |
Jul 07 07:38:24 PM PDT 24 |
3967818498 ps |
| T890 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2185140933 |
|
|
Jul 07 07:59:49 PM PDT 24 |
Jul 07 08:11:41 PM PDT 24 |
4341751344 ps |
| T1358 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1077950094 |
|
|
Jul 07 07:23:05 PM PDT 24 |
Jul 07 07:25:50 PM PDT 24 |
2999744349 ps |
| T1359 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.2129826224 |
|
|
Jul 07 07:26:49 PM PDT 24 |
Jul 07 08:40:59 PM PDT 24 |
15408699512 ps |
| T815 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3074029392 |
|
|
Jul 07 07:57:10 PM PDT 24 |
Jul 07 08:03:37 PM PDT 24 |
4099643696 ps |
| T1360 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4063656698 |
|
|
Jul 07 07:46:23 PM PDT 24 |
Jul 07 07:55:34 PM PDT 24 |
6370612340 ps |
| T264 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.4242657172 |
|
|
Jul 07 07:35:46 PM PDT 24 |
Jul 07 07:40:14 PM PDT 24 |
2758491970 ps |
| T1361 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2320304283 |
|
|
Jul 07 07:31:22 PM PDT 24 |
Jul 07 08:32:35 PM PDT 24 |
15582802120 ps |
| T1362 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695976594 |
|
|
Jul 07 07:55:38 PM PDT 24 |
Jul 07 08:03:06 PM PDT 24 |
3779156148 ps |
| T1363 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.665266352 |
|
|
Jul 07 07:59:33 PM PDT 24 |
Jul 07 08:05:46 PM PDT 24 |
3574094024 ps |
| T1364 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.753458998 |
|
|
Jul 07 07:56:42 PM PDT 24 |
Jul 07 08:02:49 PM PDT 24 |
3553371104 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_gpio.667387956 |
|
|
Jul 07 07:24:52 PM PDT 24 |
Jul 07 07:31:34 PM PDT 24 |
3496152056 ps |
| T827 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3135568701 |
|
|
Jul 07 07:57:14 PM PDT 24 |
Jul 07 08:08:44 PM PDT 24 |
5027684664 ps |
| T1365 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3541372909 |
|
|
Jul 07 07:37:29 PM PDT 24 |
Jul 07 07:48:04 PM PDT 24 |
4187312696 ps |
| T72 |
/workspace/coverage/default/4.chip_tap_straps_rma.3618500428 |
|
|
Jul 07 07:50:20 PM PDT 24 |
Jul 07 07:56:02 PM PDT 24 |
3727457553 ps |
| T1366 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.3888555075 |
|
|
Jul 07 07:39:17 PM PDT 24 |
Jul 07 08:41:47 PM PDT 24 |
14936010651 ps |
| T1367 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1328599481 |
|
|
Jul 07 07:42:24 PM PDT 24 |
Jul 07 07:55:40 PM PDT 24 |
6710949584 ps |
| T1368 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4237419000 |
|
|
Jul 07 07:27:59 PM PDT 24 |
Jul 07 08:25:16 PM PDT 24 |
11804878440 ps |
| T1369 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3218371832 |
|
|
Jul 07 07:37:03 PM PDT 24 |
Jul 07 07:54:46 PM PDT 24 |
5214059928 ps |
| T95 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.637464293 |
|
|
Jul 07 07:52:48 PM PDT 24 |
Jul 07 07:59:09 PM PDT 24 |
4025497588 ps |
| T96 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1406071946 |
|
|
Jul 07 07:52:11 PM PDT 24 |
Jul 07 08:02:00 PM PDT 24 |
4587645560 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3720810590 |
|
|
Jul 07 07:37:33 PM PDT 24 |
Jul 07 07:39:16 PM PDT 24 |
2328126208 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2042721527 |
|
|
Jul 07 07:23:08 PM PDT 24 |
Jul 07 07:26:50 PM PDT 24 |
3356842272 ps |
| T99 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.763698199 |
|
|
Jul 07 07:24:32 PM PDT 24 |
Jul 07 07:35:42 PM PDT 24 |
4308050654 ps |
| T100 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1507762383 |
|
|
Jul 07 07:49:14 PM PDT 24 |
Jul 07 08:42:08 PM PDT 24 |
11742344952 ps |
| T101 |
/workspace/coverage/default/2.rom_raw_unlock.2296790205 |
|
|
Jul 07 07:45:58 PM PDT 24 |
Jul 07 07:49:53 PM PDT 24 |
3897294652 ps |
| T102 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.397108808 |
|
|
Jul 07 07:55:38 PM PDT 24 |
Jul 07 08:01:41 PM PDT 24 |
3959203204 ps |
| T103 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.604051667 |
|
|
Jul 07 07:18:16 PM PDT 24 |
Jul 07 07:56:44 PM PDT 24 |
20926769081 ps |
| T104 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1561354372 |
|
|
Jul 07 07:26:42 PM PDT 24 |
Jul 07 07:37:15 PM PDT 24 |
3912437380 ps |
| T872 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1812286017 |
|
|
Jul 07 07:57:45 PM PDT 24 |
Jul 07 08:03:26 PM PDT 24 |
3685066456 ps |
| T1370 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.223922156 |
|
|
Jul 07 07:28:41 PM PDT 24 |
Jul 07 08:31:21 PM PDT 24 |
20855209000 ps |
| T1371 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3347439608 |
|
|
Jul 07 07:26:43 PM PDT 24 |
Jul 07 08:57:35 PM PDT 24 |
48155670906 ps |
| T1372 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3646861536 |
|
|
Jul 07 07:33:04 PM PDT 24 |
Jul 07 07:44:15 PM PDT 24 |
4289063728 ps |
| T781 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3931454699 |
|
|
Jul 07 07:40:05 PM PDT 24 |
Jul 07 07:53:36 PM PDT 24 |
4725782188 ps |
| T857 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668253111 |
|
|
Jul 07 07:51:58 PM PDT 24 |
Jul 07 08:00:26 PM PDT 24 |
3715010824 ps |
| T1373 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2632308417 |
|
|
Jul 07 07:50:40 PM PDT 24 |
Jul 07 07:59:08 PM PDT 24 |
5583592270 ps |
| T1374 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3563342293 |
|
|
Jul 07 07:41:14 PM PDT 24 |
Jul 07 07:52:54 PM PDT 24 |
7433512802 ps |
| T1375 |
/workspace/coverage/default/0.chip_sw_example_rom.4086257070 |
|
|
Jul 07 07:17:02 PM PDT 24 |
Jul 07 07:19:15 PM PDT 24 |
2458044430 ps |
| T1376 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.948774296 |
|
|
Jul 07 07:31:03 PM PDT 24 |
Jul 07 08:46:04 PM PDT 24 |
15416044280 ps |
| T1377 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.276828763 |
|
|
Jul 07 07:41:32 PM PDT 24 |
Jul 07 11:13:21 PM PDT 24 |
255089013570 ps |
| T1378 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1156033943 |
|
|
Jul 07 07:50:36 PM PDT 24 |
Jul 07 09:00:22 PM PDT 24 |
17940643462 ps |
| T746 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2465388241 |
|
|
Jul 07 07:19:26 PM PDT 24 |
Jul 07 07:28:31 PM PDT 24 |
5366149743 ps |
| T1379 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.982554298 |
|
|
Jul 07 07:27:34 PM PDT 24 |
Jul 07 07:48:41 PM PDT 24 |
10337607561 ps |
| T1380 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2425604282 |
|
|
Jul 07 07:34:00 PM PDT 24 |
Jul 07 07:37:52 PM PDT 24 |
2244258031 ps |
| T1381 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.354785906 |
|
|
Jul 07 07:24:24 PM PDT 24 |
Jul 07 10:34:30 PM PDT 24 |
64862667099 ps |
| T888 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2895591426 |
|
|
Jul 07 07:54:09 PM PDT 24 |
Jul 07 08:03:14 PM PDT 24 |
5140285288 ps |
| T1382 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3198714266 |
|
|
Jul 07 07:49:53 PM PDT 24 |
Jul 07 08:32:34 PM PDT 24 |
9110240324 ps |
| T1383 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3426578339 |
|
|
Jul 07 07:54:23 PM PDT 24 |
Jul 07 08:03:33 PM PDT 24 |
4853184154 ps |
| T1384 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.533540547 |
|
|
Jul 07 07:37:48 PM PDT 24 |
Jul 07 10:47:03 PM PDT 24 |
59032007649 ps |
| T1385 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3853098212 |
|
|
Jul 07 07:41:31 PM PDT 24 |
Jul 07 07:46:49 PM PDT 24 |
3016156480 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3839585027 |
|
|
Jul 07 07:29:06 PM PDT 24 |
Jul 07 07:36:01 PM PDT 24 |
2746649316 ps |
| T1386 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2428032948 |
|
|
Jul 07 07:46:46 PM PDT 24 |
Jul 07 08:12:38 PM PDT 24 |
7122132480 ps |
| T1387 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2788572731 |
|
|
Jul 07 07:40:19 PM PDT 24 |
Jul 07 08:45:51 PM PDT 24 |
14215108592 ps |
| T1388 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3428706663 |
|
|
Jul 07 07:37:20 PM PDT 24 |
Jul 07 07:58:29 PM PDT 24 |
6057815560 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.375058008 |
|
|
Jul 07 07:17:35 PM PDT 24 |
Jul 07 07:28:32 PM PDT 24 |
4271575360 ps |
| T1389 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1897444327 |
|
|
Jul 07 07:17:37 PM PDT 24 |
Jul 07 11:11:32 PM PDT 24 |
78391047776 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1481266188 |
|
|
Jul 07 07:25:02 PM PDT 24 |
Jul 07 07:30:55 PM PDT 24 |
4460035720 ps |
| T1390 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.112846689 |
|
|
Jul 07 07:20:55 PM PDT 24 |
Jul 07 07:29:06 PM PDT 24 |
4263622600 ps |
| T804 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3015514909 |
|
|
Jul 07 07:52:36 PM PDT 24 |
Jul 07 08:04:12 PM PDT 24 |
6092192200 ps |
| T1391 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2978132977 |
|
|
Jul 07 07:46:22 PM PDT 24 |
Jul 07 07:58:01 PM PDT 24 |
4461742500 ps |
| T153 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.635230632 |
|
|
Jul 07 07:34:39 PM PDT 24 |
Jul 07 08:18:57 PM PDT 24 |
16754445364 ps |
| T1392 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3325305102 |
|
|
Jul 07 07:28:00 PM PDT 24 |
Jul 07 08:35:39 PM PDT 24 |
14766903498 ps |
| T1393 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3902025375 |
|
|
Jul 07 07:47:23 PM PDT 24 |
Jul 07 07:58:59 PM PDT 24 |
4178989208 ps |
| T1394 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1059387411 |
|
|
Jul 07 07:42:56 PM PDT 24 |
Jul 07 07:51:20 PM PDT 24 |
10009251037 ps |
| T1395 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2071582266 |
|
|
Jul 07 07:38:42 PM PDT 24 |
Jul 07 08:06:05 PM PDT 24 |
11458281261 ps |
| T1396 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2167878857 |
|
|
Jul 07 07:24:40 PM PDT 24 |
Jul 07 07:29:56 PM PDT 24 |
2657796440 ps |
| T832 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.417702070 |
|
|
Jul 07 07:50:50 PM PDT 24 |
Jul 07 07:58:45 PM PDT 24 |
4357239608 ps |
| T1397 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.61266761 |
|
|
Jul 07 07:17:26 PM PDT 24 |
Jul 07 07:22:52 PM PDT 24 |
2569094172 ps |
| T1398 |
/workspace/coverage/default/2.rom_e2e_static_critical.2322017569 |
|
|
Jul 07 07:50:45 PM PDT 24 |
Jul 07 08:53:40 PM PDT 24 |
16593267540 ps |
| T392 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2535067882 |
|
|
Jul 07 07:39:02 PM PDT 24 |
Jul 07 07:54:17 PM PDT 24 |
4661903338 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.141196029 |
|
|
Jul 07 07:26:17 PM PDT 24 |
Jul 07 07:38:15 PM PDT 24 |
4949394500 ps |
| T1399 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.1587302524 |
|
|
Jul 07 07:29:10 PM PDT 24 |
Jul 07 07:33:46 PM PDT 24 |
3234801739 ps |
| T845 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2418689103 |
|
|
Jul 07 07:58:11 PM PDT 24 |
Jul 07 08:09:19 PM PDT 24 |
4372650680 ps |
| T1400 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695857615 |
|
|
Jul 07 07:51:39 PM PDT 24 |
Jul 07 07:58:28 PM PDT 24 |
4035515122 ps |
| T150 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4183887493 |
|
|
Jul 07 07:23:19 PM PDT 24 |
Jul 07 07:32:46 PM PDT 24 |
5883728026 ps |
| T1401 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2084371750 |
|
|
Jul 07 07:56:02 PM PDT 24 |
Jul 07 08:07:41 PM PDT 24 |
4817777360 ps |
| T1402 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.373871088 |
|
|
Jul 07 07:47:07 PM PDT 24 |
Jul 07 07:50:51 PM PDT 24 |
3121557326 ps |
| T1403 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2563638608 |
|
|
Jul 07 07:40:22 PM PDT 24 |
Jul 07 07:48:52 PM PDT 24 |
8327924357 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3202560939 |
|
|
Jul 07 07:39:22 PM PDT 24 |
Jul 07 08:11:22 PM PDT 24 |
10468333800 ps |
| T1404 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2402046110 |
|
|
Jul 07 07:30:14 PM PDT 24 |
Jul 07 08:17:41 PM PDT 24 |
9002827502 ps |
| T1405 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3350432917 |
|
|
Jul 07 07:36:12 PM PDT 24 |
Jul 07 07:40:01 PM PDT 24 |
2612381700 ps |
| T426 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1032245415 |
|
|
Jul 07 07:38:48 PM PDT 24 |
Jul 07 07:45:54 PM PDT 24 |
3595068220 ps |
| T1406 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.256013223 |
|
|
Jul 07 07:34:46 PM PDT 24 |
Jul 07 07:38:37 PM PDT 24 |
2383939160 ps |
| T1407 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3107527591 |
|
|
Jul 07 07:18:57 PM PDT 24 |
Jul 07 07:32:24 PM PDT 24 |
4484232418 ps |
| T1408 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3890354550 |
|
|
Jul 07 07:19:37 PM PDT 24 |
Jul 07 07:24:29 PM PDT 24 |
2459306102 ps |
| T1409 |
/workspace/coverage/default/4.chip_tap_straps_prod.315727094 |
|
|
Jul 07 07:49:42 PM PDT 24 |
Jul 07 07:51:47 PM PDT 24 |
2407376965 ps |
| T1410 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.568783054 |
|
|
Jul 07 07:48:56 PM PDT 24 |
Jul 07 08:27:25 PM PDT 24 |
13627583282 ps |
| T1411 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1658811163 |
|
|
Jul 07 07:46:10 PM PDT 24 |
Jul 07 08:00:57 PM PDT 24 |
4992819800 ps |
| T1412 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1976075962 |
|
|
Jul 07 07:17:28 PM PDT 24 |
Jul 07 07:50:10 PM PDT 24 |
10399078293 ps |
| T1413 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3820835664 |
|
|
Jul 07 07:46:40 PM PDT 24 |
Jul 07 07:52:25 PM PDT 24 |
3062422204 ps |
| T1414 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1274227965 |
|
|
Jul 07 07:35:54 PM PDT 24 |
Jul 07 07:57:07 PM PDT 24 |
5694937116 ps |
| T380 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3861787426 |
|
|
Jul 07 07:20:21 PM PDT 24 |
Jul 07 07:27:58 PM PDT 24 |
4858938040 ps |
| T1415 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.555704031 |
|
|
Jul 07 07:26:27 PM PDT 24 |
Jul 07 07:36:08 PM PDT 24 |
4895855600 ps |
| T886 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2791196924 |
|
|
Jul 07 07:57:55 PM PDT 24 |
Jul 07 08:05:22 PM PDT 24 |
4117385832 ps |
| T1416 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1268656861 |
|
|
Jul 07 07:45:12 PM PDT 24 |
Jul 07 07:56:57 PM PDT 24 |
10723253674 ps |
| T1417 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2053944860 |
|
|
Jul 07 07:16:39 PM PDT 24 |
Jul 07 07:20:23 PM PDT 24 |
2932976280 ps |
| T333 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.4288641016 |
|
|
Jul 07 07:42:19 PM PDT 24 |
Jul 07 08:03:49 PM PDT 24 |
6595768370 ps |
| T816 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2789114056 |
|
|
Jul 07 07:50:56 PM PDT 24 |
Jul 07 08:03:23 PM PDT 24 |
5218767608 ps |
| T1418 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.360299222 |
|
|
Jul 07 07:18:16 PM PDT 24 |
Jul 07 07:52:08 PM PDT 24 |
8849860618 ps |
| T819 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3279694794 |
|
|
Jul 07 07:24:31 PM PDT 24 |
Jul 07 07:39:20 PM PDT 24 |
5653784338 ps |
| T1419 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2707702168 |
|
|
Jul 07 07:18:58 PM PDT 24 |
Jul 07 07:43:47 PM PDT 24 |
7801806856 ps |
| T1420 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1360553014 |
|
|
Jul 07 07:39:17 PM PDT 24 |
Jul 07 08:13:11 PM PDT 24 |
25577103500 ps |