Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3763741	1			T80	2371		T81	8833		T82	55
values[2]	760051	1			T81	994		T82	38		T88	242
values[3]	103300	1			T81	75		T82	3		T88	2
values[4]	55093	1			T81	96		T510	16		T248	1
values[5]	36338	1			T81	66		T510	16		T409	120
values[6]	26662	1			T81	81		T510	16		T409	73
values[7]	21923	1			T81	79		T510	16		T409	42
values[8]	18692	1			T81	57		T510	16		T409	60
values[9]	16495	1			T81	71		T510	16		T409	90
values[10]	15327	1			T81	74		T510	16		T409	78
values[11]	13925	1			T81	82		T510	16		T409	75
values[12]	13333	1			T81	57		T510	16		T409	73
values[13]	12320	1			T81	82		T510	16		T409	71
values[14]	11740	1			T81	77		T510	16		T409	98
values[15]	11519	1			T81	96		T510	16		T409	100
values[16]	11251	1			T81	106		T510	16		T409	73
values[17]	11064	1			T81	80		T510	16		T409	74
values[18]	10353	1			T81	55		T510	16		T409	88
values[19]	9858	1			T81	56		T510	16		T409	86
values[20]	9728	1			T81	67		T510	17		T409	70
values[21]	9312	1			T81	71		T510	16		T409	93
values[22]	8814	1			T81	67		T510	16		T409	79
values[23]	8536	1			T81	67		T510	16		T409	67
values[24]	8586	1			T81	64		T510	16		T409	44
values[25]	8553	1			T81	64		T510	16		T409	57
values[26]	8064	1			T81	50		T510	17		T409	49
values[27]	7682	1			T81	47		T510	16		T409	43
values[28]	7091	1			T81	45		T510	16		T409	75
values[29]	6686	1			T81	57		T510	17		T409	79
values[30]	6167	1			T81	39		T510	16		T409	49
values[31]	5878	1			T81	41		T510	17		T409	71
values[32]	5295	1			T81	32		T510	16		T409	45
values[33]	4930	1			T81	23		T510	16		T409	19
values[34]	4670	1			T81	25		T510	16		T409	27
values[35]	4486	1			T81	21		T510	16		T409	27
values[36]	4156	1			T81	19		T510	16		T409	24
values[37]	4064	1			T81	19		T510	17		T409	29
values[38]	3888	1			T81	18		T510	16		T409	27
values[39]	3638	1			T81	23		T510	16		T409	21
values[40]	3478	1			T81	16		T510	16		T409	27
values[41]	3301	1			T81	11		T510	16		T409	18
values[42]	3246	1			T81	15		T510	16		T409	10
values[43]	3278	1			T81	16		T510	16		T409	20
values[44]	3088	1			T81	11		T510	16		T409	10
values[45]	3060	1			T81	10		T510	17		T409	6
values[46]	2959	1			T81	12		T510	16		T409	8
values[47]	2827	1			T81	11		T510	16		T409	9
values[48]	2856	1			T81	14		T510	16		T409	8
values[49]	2875	1			T81	4		T510	16		T409	9
values[50]	2814	1			T81	9		T510	16		T409	9
values[51]	2681	1			T81	6		T510	16		T409	8
values[52]	2672	1			T81	5		T510	17		T409	7
values[53]	2558	1			T81	5		T510	16		T409	9
values[54]	2516	1			T81	2		T510	17		T409	5
values[55]	2483	1			T81	5		T510	16		T409	7
values[56]	2365	1			T81	8		T510	16		T409	4
values[57]	2363	1			T81	4		T510	16		T409	1
values[58]	2336	1			T81	4		T510	16		T409	2
values[59]	2303	1			T81	2		T510	16		T409	2
values[60]	2332	1			T81	3		T510	17		T409	3
values[61]	2501	1			T81	4		T510	16		T409	4
values[62]	3680	1			T81	4		T510	17		T409	1
values[63]	9710	1			T81	9		T510	16		T409	6
values[64]	226680	1			T81	189		T510	2838		T409	109

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4772135	1			T80	2496		T81	10881		T82	98
values[2]	810017	1			T81	1511		T82	31		T88	234
values[3]	85239	1			T81	27		T82	3		T88	5
values[4]	14951	1			T81	12		T88	1		T389	2
values[5]	5701	1			T81	4		T510	24		T409	2
values[6]	3451	1			T81	3		T510	10		T409	2
values[7]	2624	1			T81	3		T510	5		T409	3
values[8]	2328	1			T81	5		T510	3		T409	5
values[9]	1998	1			T81	3		T510	2		T409	3
values[10]	1814	1			T81	3		T510	2		T409	1
values[11]	1634	1			T81	2		T510	2		T409	1
values[12]	1502	1			T81	5		T510	2		T409	1
values[13]	1455	1			T81	5		T510	2		T409	1
values[14]	1320	1			T81	4		T510	2		T409	1
values[15]	1273	1			T81	3		T510	2		T409	2
values[16]	1187	1			T81	8		T510	2		T409	2
values[17]	1064	1			T81	6		T510	2		T409	1
values[18]	1014	1			T81	3		T510	2		T409	1
values[19]	940	1			T81	7		T510	2		T409	2
values[20]	942	1			T81	4		T510	2		T409	1
values[21]	889	1			T81	2		T510	2		T409	1
values[22]	857	1			T81	3		T510	2		T409	2
values[23]	819	1			T81	5		T510	2		T409	1
values[24]	768	1			T81	4		T510	2		T409	1
values[25]	717	1			T81	3		T510	2		T409	1
values[26]	719	1			T81	3		T510	2		T409	2
values[27]	690	1			T81	5		T510	2		T409	1
values[28]	586	1			T81	5		T510	2		T409	1
values[29]	658	1			T81	4		T510	2		T409	5
values[30]	576	1			T81	9		T510	2		T409	5
values[31]	567	1			T81	6		T510	2		T409	2
values[32]	520	1			T81	5		T510	2		T409	1
values[33]	521	1			T81	3		T510	2		T409	2
values[34]	534	1			T81	3		T510	2		T409	2
values[35]	499	1			T81	3		T510	2		T409	1
values[36]	455	1			T81	4		T510	2		T409	2
values[37]	451	1			T81	2		T510	2		T409	2
values[38]	449	1			T81	4		T510	2		T409	1
values[39]	441	1			T81	2		T510	2		T409	4
values[40]	477	1			T81	5		T510	2		T409	3
values[41]	439	1			T81	5		T510	2		T409	1
values[42]	436	1			T81	4		T510	2		T409	2
values[43]	425	1			T81	5		T510	2		T409	3
values[44]	390	1			T81	4		T510	3		T409	1
values[45]	381	1			T81	3		T510	2		T409	2
values[46]	371	1			T81	2		T510	2		T409	5
values[47]	375	1			T81	4		T510	2		T409	1
values[48]	380	1			T81	2		T510	2		T409	1
values[49]	392	1			T81	2		T510	2		T409	2
values[50]	363	1			T81	3		T510	2		T409	2
values[51]	365	1			T81	6		T510	2		T409	1
values[52]	344	1			T81	3		T510	2		T409	2
values[53]	334	1			T81	4		T510	2		T409	1
values[54]	349	1			T81	2		T510	2		T409	1
values[55]	351	1			T81	3		T510	2		T409	2
values[56]	370	1			T81	5		T510	2		T409	1
values[57]	336	1			T81	5		T510	2		T409	3
values[58]	313	1			T81	2		T510	2		T409	3
values[59]	322	1			T81	2		T510	2		T409	2
values[60]	332	1			T81	3		T510	2		T409	3
values[61]	340	1			T81	3		T510	2		T409	3
values[62]	511	1			T81	5		T510	2		T409	3
values[63]	1731	1			T81	25		T510	2		T409	11
values[64]	26632	1			T81	289		T510	341		T409	144

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	589356	1			T80	2407		T81	777		T82	1
values[2]	2660095	1			T81	8270		T82	62		T88	946
values[3]	1213564	1			T81	971		T82	57		T88	225
values[4]	149526	1			T81	87		T82	3		T389	1
values[5]	77128	1			T81	86		T510	16		T248	1
values[6]	50407	1			T81	76		T510	16		T409	75
values[7]	35638	1			T81	59		T510	16		T409	77
values[8]	28275	1			T81	85		T510	16		T409	84
values[9]	23540	1			T81	94		T510	16		T409	108
values[10]	20127	1			T81	96		T510	17		T409	62
values[11]	18171	1			T81	98		T510	16		T409	66
values[12]	16353	1			T81	84		T510	16		T409	81
values[13]	15415	1			T81	91		T510	16		T409	81
values[14]	14928	1			T81	68		T510	16		T409	81
values[15]	14217	1			T81	94		T510	16		T409	85
values[16]	13612	1			T81	81		T510	16		T409	78
values[17]	12676	1			T81	75		T510	17		T409	82
values[18]	12105	1			T81	70		T510	16		T409	64
values[19]	11689	1			T81	54		T510	17		T409	62
values[20]	11491	1			T81	61		T510	16		T409	66
values[21]	10828	1			T81	87		T510	16		T409	75
values[22]	10289	1			T81	73		T510	16		T409	70
values[23]	10106	1			T81	84		T510	16		T409	70
values[24]	9737	1			T81	79		T510	16		T409	96
values[25]	9172	1			T81	74		T510	16		T409	38
values[26]	8646	1			T81	62		T510	16		T409	41
values[27]	8061	1			T81	72		T510	16		T409	53
values[28]	7510	1			T81	43		T510	16		T409	75
values[29]	7141	1			T81	45		T510	16		T409	88
values[30]	6776	1			T81	58		T510	17		T409	91
values[31]	6369	1			T81	44		T510	16		T409	101
values[32]	5815	1			T81	34		T510	16		T409	69
values[33]	5355	1			T81	23		T510	16		T409	50
values[34]	5243	1			T81	27		T510	16		T409	45
values[35]	4914	1			T81	34		T510	16		T409	30
values[36]	4606	1			T81	32		T510	17		T409	26
values[37]	4250	1			T81	22		T510	16		T409	25
values[38]	3971	1			T81	17		T510	16		T409	28
values[39]	3733	1			T81	11		T510	17		T409	14
values[40]	3582	1			T81	17		T510	16		T409	9
values[41]	3458	1			T81	15		T510	17		T409	5
values[42]	3378	1			T81	10		T510	18		T409	6
values[43]	3409	1			T81	13		T510	16		T409	2
values[44]	3275	1			T81	14		T510	16		T409	7
values[45]	3190	1			T81	12		T510	16		T409	6
values[46]	3148	1			T81	8		T510	16		T409	7
values[47]	3072	1			T81	10		T510	16		T409	8
values[48]	3160	1			T81	10		T510	16		T409	2
values[49]	3053	1			T81	13		T510	16		T409	2
values[50]	3102	1			T81	8		T510	16		T409	3
values[51]	3023	1			T81	7		T510	16		T409	1
values[52]	2996	1			T81	13		T510	16		T409	1
values[53]	2852	1			T81	9		T510	16		T409	2
values[54]	2798	1			T81	10		T510	16		T409	2
values[55]	2804	1			T81	10		T510	16		T409	1
values[56]	2734	1			T81	3		T510	17		T409	2
values[57]	2616	1			T81	3		T510	16		T409	1
values[58]	2675	1			T81	2		T510	16		T409	1
values[59]	2568	1			T81	4		T510	16		T409	1
values[60]	2558	1			T81	2		T510	16		T409	1
values[61]	2650	1			T81	5		T510	16		T409	1
values[62]	3532	1			T81	3		T510	16		T409	2
values[63]	8519	1			T81	2		T510	18		T409	4
values[64]	222392	1			T81	339		T510	3213		T409	145