Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1867537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36415639

1

T4

16369

T5

375990

T6

27011

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26732651	1			T4	5168		T5	351613		T6	10515
values[0x0]	10207735	1			T4	11201		T5	24377		T6	16496
values[0x1]	1342790	1			T4	717		T5	104		T6	1477

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	630471	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37652705

1

T4

17086

T5

376094

T6

28488

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17990544	1			T4	8544		T5	188048		T6	14246
valid_sources[0x01]	17990498	1			T4	8542		T5	188046		T6	14242
valid_sources[0x02]	36840	1			T203	2		T522	3		T149	377
valid_sources[0x03]	37706	1			T87	1		T522	4		T149	410
valid_sources[0x04]	36902	1			T85	1		T522	1		T149	442
valid_sources[0x05]	37352	1			T87	3		T9	1		T203	1
valid_sources[0x06]	36715	1			T87	1		T522	1		T149	404
valid_sources[0x07]	36377	1			T85	1		T87	1		T203	1
valid_sources[0x08]	37146	1			T85	2		T522	1		T149	440
valid_sources[0x09]	36472	1			T522	1		T149	403		T357	748
valid_sources[0x0a]	36575	1			T9	1		T203	2		T522	4
valid_sources[0x0b]	37848	1			T87	2		T203	1		T522	2
valid_sources[0x0c]	36990	1			T85	3		T9	2		T522	1
valid_sources[0x0d]	39935	1			T522	2		T149	439		T357	735
valid_sources[0x0e]	37358	1			T87	3		T9	1		T203	2
valid_sources[0x0f]	36666	1			T85	2		T9	1		T149	433
valid_sources[0x10]	37084	1			T85	1		T87	1		T522	3
valid_sources[0x11]	37577	1			T87	1		T9	1		T522	3
valid_sources[0x12]	37523	1			T85	3		T203	2		T522	4
valid_sources[0x13]	37168	1			T85	1		T9	1		T202	39
valid_sources[0x14]	37438	1			T9	2		T149	414		T357	678
valid_sources[0x15]	38399	1			T522	4		T149	396		T357	718
valid_sources[0x16]	37219	1			T85	1		T87	1		T9	2
valid_sources[0x17]	37335	1			T87	1		T522	3		T149	387
valid_sources[0x18]	36372	1			T87	1		T9	3		T203	1
valid_sources[0x19]	37662	1			T85	1		T9	2		T522	2
valid_sources[0x1a]	37879	1			T85	2		T87	1		T203	1
valid_sources[0x1b]	37275	1			T87	1		T149	363		T357	709
valid_sources[0x1c]	36866	1			T9	1		T203	1		T522	2
valid_sources[0x1d]	37452	1			T87	1		T9	1		T522	5
valid_sources[0x1e]	37953	1			T87	1		T203	1		T522	6
valid_sources[0x1f]	36332	1			T85	5		T87	1		T522	3
valid_sources[0x20]	37181	1			T203	1		T149	417		T357	692

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26013060

1

T4

5168

T5

351613

T6

10515

values[0x0]

all_enables

biggest_size

10166647

1

T4

11201

T5

24377

T6

16496

values[0x1]

all_enables

biggest_size

235932

1

T85

18

T86

18

T87

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2951533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465782

1

T80

310

T81

49

T82

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1157055	1			T80	829		T81	260		T82	37
values[0x0]	1103866	1			T80	787		T81	37		T82	27
values[0x1]	1156394	1			T80	755		T81	215		T82	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2287629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1129686

1

T80

771

T81

193

T82

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53445	1			T80	33		T81	14		T82	1
valid_sources[0x01]	53200	1			T80	60		T81	5		T82	3
valid_sources[0x02]	55189	1			T80	56		T81	12		T88	1
valid_sources[0x03]	52767	1			T80	77		T81	5		T82	5
valid_sources[0x04]	52994	1			T80	48		T81	9		T82	4
valid_sources[0x05]	53784	1			T80	10		T81	8		T82	3
valid_sources[0x06]	53046	1			T80	30		T81	7		T82	3
valid_sources[0x07]	53476	1			T80	11		T81	11		T88	1
valid_sources[0x08]	54154	1			T80	29		T81	6		T389	71
valid_sources[0x09]	53757	1			T80	25		T81	6		T88	1
valid_sources[0x0a]	53331	1			T80	28		T81	4		T88	4
valid_sources[0x0b]	54336	1			T80	12		T81	7		T389	24
valid_sources[0x0c]	53624	1			T80	51		T81	7		T389	76
valid_sources[0x0d]	52225	1			T80	92		T81	17		T88	1
valid_sources[0x0e]	54117	1			T80	31		T81	9		T389	44
valid_sources[0x0f]	53901	1			T80	43		T81	5		T82	4
valid_sources[0x10]	53449	1			T80	15		T81	8		T82	3
valid_sources[0x11]	53039	1			T80	10		T81	5		T389	45
valid_sources[0x12]	52957	1			T80	12		T81	5		T82	1
valid_sources[0x13]	53423	1			T80	33		T81	9		T88	1
valid_sources[0x14]	52923	1			T81	4		T82	2		T88	1
valid_sources[0x15]	53359	1			T80	15		T81	10		T88	1
valid_sources[0x16]	54516	1			T80	12		T81	5		T82	5
valid_sources[0x17]	53066	1			T80	45		T81	8		T82	4
valid_sources[0x18]	53528	1			T80	19		T81	6		T88	4
valid_sources[0x19]	53751	1			T80	59		T81	13		T82	3
valid_sources[0x1a]	54002	1			T80	8		T81	10		T82	7
valid_sources[0x1b]	53159	1			T80	43		T81	13		T389	27
valid_sources[0x1c]	53664	1			T80	56		T81	4		T88	1
valid_sources[0x1d]	54179	1			T80	40		T81	6		T82	3
valid_sources[0x1e]	53037	1			T80	26		T81	5		T389	21
valid_sources[0x1f]	52397	1			T80	35		T81	6		T82	3
valid_sources[0x20]	53353	1			T80	54		T81	6		T389	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49085

1

T80

29

T81

24

T389

22

values[0x0]

all_enables

biggest_size

368054

1

T80

253

T81

11

T82

5

values[0x1]

all_enables

biggest_size

48643

1

T80

28

T81

14

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3137009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

510414

1

T80

369

T81

74

T82

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1246213	1			T80	830		T81	264		T82	49
values[0x0]	1152898	1			T80	835		T81	54		T82	30
values[0x1]	1248312	1			T80	831		T81	297		T82	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2409175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1238248

1

T80

876

T81

253

T82

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57865	1			T80	24		T81	12		T389	41
valid_sources[0x01]	57081	1			T80	68		T81	6		T82	5
valid_sources[0x02]	57040	1			T80	51		T81	9		T88	2
valid_sources[0x03]	56247	1			T80	95		T81	15		T82	3
valid_sources[0x04]	57588	1			T80	56		T81	7		T82	1
valid_sources[0x05]	57606	1			T80	6		T81	6		T88	2
valid_sources[0x06]	57630	1			T80	21		T81	11		T82	5
valid_sources[0x07]	56734	1			T80	12		T81	14		T389	35
valid_sources[0x08]	57419	1			T80	49		T81	5		T389	35
valid_sources[0x09]	57443	1			T80	23		T81	11		T389	31
valid_sources[0x0a]	55703	1			T80	30		T81	5		T88	2
valid_sources[0x0b]	57698	1			T80	7		T81	13		T82	6
valid_sources[0x0c]	57365	1			T80	68		T81	5		T82	4
valid_sources[0x0d]	56583	1			T80	120		T81	3		T82	12
valid_sources[0x0e]	58497	1			T80	36		T81	12		T82	4
valid_sources[0x0f]	58458	1			T80	48		T81	11		T88	3
valid_sources[0x10]	57345	1			T80	18		T81	10		T389	42
valid_sources[0x11]	56224	1			T80	7		T81	7		T389	37
valid_sources[0x12]	56637	1			T80	19		T81	9		T389	46
valid_sources[0x13]	56369	1			T80	29		T81	12		T88	3
valid_sources[0x14]	57144	1			T81	9		T82	6		T88	1
valid_sources[0x15]	57457	1			T80	25		T81	16		T389	36
valid_sources[0x16]	57883	1			T80	15		T81	11		T389	31
valid_sources[0x17]	56298	1			T80	67		T81	8		T82	14
valid_sources[0x18]	57652	1			T80	18		T81	8		T82	17
valid_sources[0x19]	57500	1			T80	37		T81	6		T389	34
valid_sources[0x1a]	56688	1			T80	7		T81	9		T88	1
valid_sources[0x1b]	56522	1			T80	42		T81	14		T82	3
valid_sources[0x1c]	56623	1			T80	30		T81	10		T88	2
valid_sources[0x1d]	56697	1			T80	36		T81	10		T82	1
valid_sources[0x1e]	56102	1			T80	31		T81	13		T389	29
valid_sources[0x1f]	55720	1			T80	56		T81	10		T389	39
valid_sources[0x20]	57405	1			T80	67		T81	12		T82	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53435

1

T80

37

T81

23

T82

3

values[0x0]

all_enables

biggest_size

403663

1

T80

298

T81

30

T82

8

values[0x1]

all_enables

biggest_size

53316

1

T80

34

T81

21

T82

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2985619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

472149

1

T80

347

T81

59

T82

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1170717	1			T80	805		T81	280		T82	43
values[0x0]	1118331	1			T80	822		T81	45		T82	39
values[0x1]	1168720	1			T80	780		T81	288		T82	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2310993	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1146775

1

T80

799

T81

225

T82

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54482	1			T80	26		T81	8		T88	1
valid_sources[0x01]	54102	1			T80	50		T81	12		T88	2
valid_sources[0x02]	55503	1			T80	52		T81	12		T82	6
valid_sources[0x03]	53707	1			T80	80		T81	9		T389	34
valid_sources[0x04]	53097	1			T80	37		T81	9		T389	63
valid_sources[0x05]	53957	1			T80	17		T81	9		T88	1
valid_sources[0x06]	54130	1			T80	32		T81	14		T82	7
valid_sources[0x07]	53422	1			T80	18		T81	11		T389	20
valid_sources[0x08]	54112	1			T80	34		T81	7		T82	1
valid_sources[0x09]	54352	1			T80	36		T81	4		T389	35
valid_sources[0x0a]	54038	1			T80	27		T81	8		T82	1
valid_sources[0x0b]	54435	1			T80	10		T81	7		T82	2
valid_sources[0x0c]	54330	1			T80	54		T81	9		T88	1
valid_sources[0x0d]	52924	1			T80	92		T81	5		T389	19
valid_sources[0x0e]	55294	1			T80	21		T81	8		T389	31
valid_sources[0x0f]	54243	1			T80	73		T81	8		T389	46
valid_sources[0x10]	54057	1			T80	9		T81	7		T88	1
valid_sources[0x11]	54886	1			T80	10		T81	11		T82	4
valid_sources[0x12]	53558	1			T80	12		T81	7		T82	6
valid_sources[0x13]	53381	1			T80	28		T81	8		T82	1
valid_sources[0x14]	53934	1			T81	7		T82	2		T389	48
valid_sources[0x15]	53545	1			T80	35		T81	10		T389	24
valid_sources[0x16]	53894	1			T80	5		T81	7		T389	28
valid_sources[0x17]	53968	1			T80	65		T81	13		T389	21
valid_sources[0x18]	54317	1			T80	26		T81	6		T389	39
valid_sources[0x19]	54112	1			T80	47		T81	11		T82	1
valid_sources[0x1a]	53293	1			T80	18		T81	12		T88	1
valid_sources[0x1b]	54773	1			T80	41		T81	11		T88	1
valid_sources[0x1c]	53704	1			T80	33		T81	14		T82	2
valid_sources[0x1d]	54306	1			T80	43		T81	14		T389	41
valid_sources[0x1e]	54283	1			T80	39		T81	11		T82	2
valid_sources[0x1f]	53625	1			T80	40		T81	6		T82	1
valid_sources[0x20]	54159	1			T80	53		T81	14		T389	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49106

1

T80

32

T81

16

T82

2

values[0x0]

all_enables

biggest_size

373700

1

T80

285

T81

27

T82

11

values[0x1]

all_enables

biggest_size

49343

1

T80

30

T81

16

T82

2