Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	79.17			79.17
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	91.67			91.67
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17			79.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67			91.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67			91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.97	99.83	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.47	98.93	85.82	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T62,T243	Yes	T60,T62,T243	INPUT
alert_req_i	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	INPUT
alert_ack_o	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	OUTPUT
alert_state_o	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T60,T62,T89	Yes	T60,T62,T89	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	INPUT
alert_rx_i.ping_p	Yes	Yes	T90,T91,T92	Yes	T90,T91,T92	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T60,T62,T89	Yes	T60,T62,T89	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	19	79.17
Total Bits 0->1	12	10	83.33
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	19	79.17
Port Bits 0->1	12	10	83.33
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_req_i	No	No		Yes	T376	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T92	Yes	T91,T92,T93	INPUT
alert_rx_i.ping_p	Yes	Yes	T91,T92,T93	Yes	T90,T91,T92	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	22	91.67
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	22	91.67
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_req_i	No	No		Yes	T290,T422,T423	INPUT
alert_ack_o	Yes	Yes	T290,T422,T423	Yes	T290,T422,T423	OUTPUT
alert_state_o	No	No		Yes	T290,T422,T423	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_rx_i.ping_p	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
alert_req_i	Yes	Yes	T98,T99,T100	Yes	T89,T98,T99	INPUT
alert_ack_o	Yes	Yes	T89,T98,T99	Yes	T89,T98,T99	OUTPUT
alert_state_o	Yes	Yes	T98,T99,T100	Yes	T89,T98,T99	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T62,T89,T90	Yes	T62,T89,T90	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T92	Yes	T91,T92,T93	INPUT
alert_rx_i.ping_p	Yes	Yes	T91,T92,T93	Yes	T90,T91,T92	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T62,T89,T90	Yes	T62,T89,T90	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T62,T9,T63	Yes	T62,T9,T63	INPUT
alert_req_i	Yes	Yes	T677,T678	Yes	T677,T678	INPUT
alert_ack_o	Yes	Yes	T677,T678	Yes	T677,T678	OUTPUT
alert_state_o	Yes	Yes	T677,T678	Yes	T677,T678	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T93	Yes	T91,T93,T256	INPUT
alert_rx_i.ping_p	Yes	Yes	T91,T93,T256	Yes	T90,T91,T93	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T60,T62,T243	Yes	T60,T62,T243	INPUT
alert_req_i	Yes	Yes	T9	Yes	T9	INPUT
alert_ack_o	Yes	Yes	T9	Yes	T9	OUTPUT
alert_state_o	Yes	Yes	T9	Yes	T9	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T60,T62,T90	Yes	T60,T62,T90	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_rx_i.ping_p	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T60,T62,T90	Yes	T60,T62,T90	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T62,T9,T63	Yes	T62,T9,T63	INPUT
alert_req_i	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	INPUT
alert_ack_o	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	OUTPUT
alert_state_o	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	INPUT
alert_rx_i.ping_n	Yes	Yes	T90,T91,T93	Yes	T93,T256,T257	INPUT
alert_rx_i.ping_p	Yes	Yes	T93,T256,T257	Yes	T90,T91,T93	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T181,T182,T240	Yes	T181,T182,T240	OUTPUT