Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526447682	61557020	0	0
DepthKnown_A	526447682	526339554	0	0
RvalidKnown_A	526447682	526339554	0	0
WreadyKnown_A	526447682	526339554	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	61557020	0	0
T4	107748	31705	0	0
T5	545044	356414	0	0
T6	634903	67202	0	0
T18	167823	18386	0	0
T19	158445	21263	0	0
T20	248607	126927	0	0
T21	0	9920	0	0
T61	40592	0	0	0
T95	379324	46882	0	0
T96	330056	42741	0	0
T97	201634	278431	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526447682	47710507	0	0
DepthKnown_A	526447682	526339554	0	0
RvalidKnown_A	526447682	526339554	0	0
WreadyKnown_A	526447682	526339554	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	47710507	0	0
T4	107748	23219	0	0
T5	545044	352221	0	0
T6	634903	49751	0	0
T18	167823	14471	0	0
T19	158445	16188	0	0
T20	248607	63647	0	0
T21	0	8042	0	0
T61	40592	0	0	0
T95	379324	37095	0	0
T96	330056	37834	0	0
T97	201634	251435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526447682	42709608	0	0
DepthKnown_A	526447682	526339554	0	0
RvalidKnown_A	526447682	526339554	0	0
WreadyKnown_A	526447682	526339554	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	42709608	0	0
T4	107748	17663	0	0
T5	545044	376836	0	0
T6	634903	29330	0	0
T18	167823	15449	0	0
T19	158445	9667	0	0
T20	248607	11326	0	0
T21	0	6135	0	0
T61	40592	0	0	0
T95	379324	45035	0	0
T96	330056	33015	0	0
T97	201634	550623	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526447682	35973316	0	0
DepthKnown_A	526447682	526339554	0	0
RvalidKnown_A	526447682	526339554	0	0
WreadyKnown_A	526447682	526339554	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	35973316	0	0
T4	107748	17086	0	0
T5	545044	376094	0	0
T6	634903	28488	0	0
T18	167823	15243	0	0
T19	158445	9399	0	0
T20	248607	10546	0	0
T21	0	6018	0	0
T61	40592	0	0	0
T95	379324	42427	0	0
T96	330056	32265	0	0
T97	201634	549943	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	526339554	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	90088	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	90088	0	0
T4	107748	63	0	0
T5	545044	27	0	0
T6	634903	112	0	0
T18	167823	53	0	0
T19	158445	26	0	0
T20	248607	44	0	0
T21	0	15	0	0
T61	40592	0	0	0
T95	379324	14	0	0
T96	330056	740	0	0
T97	201634	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	92563	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	92563	0	0
T4	107748	63	0	0
T5	545044	27	0	0
T6	634903	112	0	0
T18	167823	53	0	0
T19	158445	26	0	0
T20	248607	44	0	0
T21	0	15	0	0
T61	40592	0	0	0
T95	379324	14	0	0
T96	330056	740	0	0
T97	201634	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	52220	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	52220	0	0
T4	107748	59	0	0
T5	545044	25	0	0
T6	634903	97	0	0
T18	167823	52	0	0
T19	158445	23	0	0
T20	248607	39	0	0
T21	0	14	0	0
T61	40592	0	0	0
T95	379324	13	0	0
T96	330056	507	0	0
T97	201634	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	52220	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	52220	0	0
T4	107748	59	0	0
T5	545044	25	0	0
T6	634903	97	0	0
T18	167823	52	0	0
T19	158445	23	0	0
T20	248607	39	0	0
T21	0	14	0	0
T61	40592	0	0	0
T95	379324	13	0	0
T96	330056	507	0	0
T97	201634	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	37868	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	37868	0	0
T4	107748	4	0	0
T5	545044	2	0	0
T6	634903	15	0	0
T18	167823	1	0	0
T19	158445	3	0	0
T20	248607	5	0	0
T21	0	1	0	0
T61	40592	0	0	0
T95	379324	1	0	0
T96	330056	233	0	0
T97	201634	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	607017684	40343	0	0
DepthKnown_A	607017684	606897764	0	0
RvalidKnown_A	607017684	606897764	0	0
WreadyKnown_A	607017684	606897764	0	0
gen_passthru_fifo.paramCheckPass	2900	2900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	40343	0	0
T4	107748	4	0	0
T5	545044	2	0	0
T6	634903	15	0	0
T18	167823	1	0	0
T19	158445	3	0	0
T20	248607	5	0	0
T21	0	1	0	0
T61	40592	0	0	0
T95	379324	1	0	0
T96	330056	233	0	0
T97	201634	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607017684	606897764	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2900	2900	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0