Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T151,T60	Yes	T18,T151,T60	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T151,T60	Yes	T18,T151,T60	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_valid	Yes	Yes	T18,T151,T60	Yes	T18,T151,T60	INPUT
tl_o.a_ready	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T151,T54	Yes	T18,T151,T54	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T254,*T85,*T255	Yes	T254,T85,T255	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T151,*T261	Yes	T18,T151,T261	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T113,T62,T709	Yes	T113,T62,T709	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T709,T90,T710	Yes	T90,T91,T92	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T91,T92	Yes	T709,T90,T710	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T113,T62,T709	Yes	T113,T62,T709	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T151,T54	Yes	T18,T151,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T151,T152	Yes	T18,T151,T152	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T151,T152	Yes	T18,T151,T152	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T151,T152	Yes	T18,T151,T152	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T151,T261	Yes	T18,T151,T261	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_valid	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	INPUT
tl_o.a_ready	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T54,T57	Yes	T18,T54,T57	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T254,*T85,*T255	Yes	T254,T85,T255	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T261,*T54	Yes	T18,T261,T54	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T695,T90	Yes	T62,T695,T90	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T91,T93	Yes	T90,T93,T256	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T93,T256	Yes	T90,T91,T93	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T695,T90	Yes	T62,T695,T90	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T18,T54,T57	Yes	T18,T54,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T219,T220	Yes	T18,T219,T220	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T219,T220	Yes	T18,T219,T220	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T219,T220	Yes	T18,T219,T220	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T261,T219	Yes	T18,T261,T219	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T261,T219	Yes	T18,T261,T219	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_valid	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	INPUT
tl_o.a_ready	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T62,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T114,T214,T215	Yes	T114,T62,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T114,*T214,*T215	Yes	T114,T214,T215	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T113,T62,T709	Yes	T113,T62,T709	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T709,T90,T91	Yes	T90,T91,T92	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T91,T92	Yes	T709,T90,T91	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T113,T62,T709	Yes	T113,T62,T709	OUTPUT
cio_rx_i	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	INPUT
cio_tx_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
intr_tx_empty_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
intr_rx_watermark_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
intr_tx_done_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_valid	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	INPUT
tl_o.a_ready	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T62	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T62	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T152,*T316	Yes	T151,T152,T316	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T91,T93	Yes	T90,T91,T93	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T90,T91	Yes	T62,T90,T91	OUTPUT
cio_rx_i	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	INPUT
cio_tx_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
intr_tx_done_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_i.a_valid	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	INPUT
tl_o.a_ready	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T62,T28,T94	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T94,T305	Yes	T62,T28,T94	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T94,*T305	Yes	T28,T94,T305	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T108,T90	Yes	T62,T108,T90	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T710,T91	Yes	T90,T91,T92	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T91,T92	Yes	T90,T710,T91	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T108,T90	Yes	T62,T108,T90	OUTPUT
cio_rx_i	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	INPUT
cio_tx_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT

*Tests covering at least one bit in the range