Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T80,T82,T247	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T81,T88,T248	Yes	T81,T88,T248	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T65,T221,T222	Yes	T65,T221,T222	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T181,T105	Yes	T65,T181,T105	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T86,T203,T81	Yes	T86,T203,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T86,T203,T80	Yes	T86,T203,T80	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T6,T66,T181	Yes	T6,T66,T181	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T5,T83,T84	Yes	T5,T83,T84	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T5,T83,T84	Yes	T5,T83,T84	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T5,T83,T84	Yes	T5,T83,T84	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T5,T83,T84	Yes	T5,T83,T84	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T83,T254	Yes	T5,T83,T254	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T83,T84,T254	Yes	T83,T84,T254	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T5,T83,T84	Yes	T5,T83,T84	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T9,T80,T82	Yes	T9,T80,T81	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T9,T80,T81	Yes	T9,T80,T81	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T9,T80,T81	Yes	T9,T80,T81	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T84,*T254,*T255	Yes	T84,T254,T255	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T84,T254,T255	Yes	T84,T254,T255	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T84,*T254,*T255	Yes	T84,T254,T255	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T84,T254,T86	Yes	T84,T254,T86	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T5,T54,T57	Yes	T5,T54,T57	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T54,T57,T111	Yes	T54,T57,T111	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T62,T9,T63	Yes	T62,T9,T63	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T62,T9,T63	Yes	T62,T9,T63	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T21,T116,T266	Yes	T21,T116,T266	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T80,T81	Yes	T62,T9,T63	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T21,T116,T266	Yes	T21,T116,T62	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T9,T80,*T81	Yes	T9,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T21,*T266,*T332	Yes	T21,T116,T266	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T21,T116,T62	Yes	T21,T116,T62	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T65,T159,T158	Yes	T65,T159,T158	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T197,T198,T199	Yes	T197,T198,T199	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T80,T81,T389	Yes	T80,T81,T389	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T155,T25,T26	Yes	T155,T25,T26	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T155,T25,T26	Yes	T62,T155,T25	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T155,T25,T26	Yes	T155,T25,T26	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T155,*T25,*T26	Yes	T155,T25,T26	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T62,T155,T25	Yes	T62,T155,T25	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T155,T156,T86	Yes	T155,T156,T86	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T155,T156,T377	Yes	T62,T155,T156	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T155,T156,T52	Yes	T155,T156,T52	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T155,*T156,*T377	Yes	T155,T156,T377	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T62,T155,T156	Yes	T62,T155,T156	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T30,T1,T2	Yes	T30,T1,T2	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	INPUT
tl_usbdev_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T174,T33,T377	Yes	T174,T33,T377	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T174,T33,T377	Yes	T174,T33,T377	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T174,T30,T1	Yes	T174,T30,T2	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T174,*T30,*T1	Yes	T174,T30,T2	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T174,T30,T1	Yes	T174,T30,T1	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T80,T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T80,T82,T247	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T6,T95,T20	Yes	T6,T95,T20	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T272,T697,T698	Yes	T272,T697,T698	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	INPUT
tl_hmac_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	INPUT
tl_hmac_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T272,*T54,*T57	Yes	T272,T54,T57	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T272,T54,T57	Yes	T272,T54,T57	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T20,T430,T173	Yes	T20,T430,T173	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T20,T430,T173	Yes	T20,T430,T173	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T430,T431,T432	Yes	T430,T431,T432	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	INPUT
tl_kmac_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T20,T430,T153	Yes	T20,T430,T431	INPUT
tl_kmac_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T20,*T430,*T153	Yes	T20,T430,T431	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T20,T430,T153	Yes	T20,T430,T153	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T96,T661,T153	Yes	T96,T661,T153	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T96,T661,T153	Yes	T96,T661,T153	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T96,T661,T153	Yes	T96,T661,T153	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	INPUT
tl_aes_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	INPUT
tl_aes_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T661	Yes	T96,T97,T661	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T96,T97,T661	Yes	T96,T97,T661	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T88	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T88	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T20,*T96,*T97	Yes	T20,T96,T97	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T20,*T96,*T97	Yes	T20,T96,T97	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T20,*T96,*T97	Yes	T20,T96,T97	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_edn1_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_edn1_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T20,*T96,*T97	Yes	T20,T96,T97	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T20,T96,T97	Yes	T20,T96,T97	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T6,*T18,*T19	Yes	T6,T18,T19	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T87,*T202,*T203	Yes	T87,T202,T203	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	INPUT
tl_otbn_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	INPUT
tl_otbn_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T87,*T202,*T203	Yes	T87,T202,T203	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T122	Yes	T96,T97,T122	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T96,T97,T122	Yes	T96,T97,T122	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	INPUT
tl_keymgr_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T60,*T153,*T173	Yes	T60,T153,T173	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T60,T153,T173	Yes	T60,T153,T173	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T254,*T255,*T9	Yes	T254,T255,T9	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T9,T81,T82	Yes	T9,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T20,T96	Yes	T6,T20,T96	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T20,T96	Yes	T6,T20,T96	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T254,T255,T9	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T86,*T420,*T421	Yes	T86,T420,T421	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T186,T295,T296	Yes	T186,T295,T296	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T182,T54,T55	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T182,T54,T55	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T420,T421	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T182,*T183,*T186	Yes	T182,T240,T115	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T182,T240,T54	Yes	T182,T240,T54	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range