Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	90.32		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T65,T159,T158	Yes	T65,T159,T158	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T18,T60,T261	Yes	T18,T60,T261	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	INPUT
tl_uart0_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T18,T54,T57	Yes	T18,T54,T57	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	INPUT
tl_uart0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T254,*T85,*T255	Yes	T254,T85,T255	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T18,*T261,*T54	Yes	T18,T261,T54	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T18,T261,T54	Yes	T18,T261,T54	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	INPUT
tl_uart1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T214,T215	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T114,T214,T215	Yes	T114,T62,T214	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T114,T214,T215	Yes	T114,T62,T214	INPUT
tl_uart1_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T114,*T214,*T215	Yes	T114,T214,T215	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T114,T62,T214	Yes	T114,T62,T214	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	INPUT
tl_uart2_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T316	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T62	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T151,T152,T316	Yes	T151,T152,T62	INPUT
tl_uart2_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T151,*T152,*T316	Yes	T151,T152,T316	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T151,T152,T62	Yes	T151,T152,T62	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	INPUT
tl_uart3_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T28,T94,T305	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T94,T305	Yes	T62,T28,T94	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T28,T94,T305	Yes	T62,T28,T94	INPUT
tl_uart3_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T28,*T94,*T305	Yes	T28,T94,T305	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T62,T28,T94	Yes	T62,T28,T94	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_i2c0_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T303,T304,T309	Yes	T52,T53,T303	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T52,*T365,*T53	Yes	T52,T365,T53	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_i2c1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T303,T304,T309	Yes	T303,T304,T309	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T52,*T365,*T53	Yes	T52,T365,T53	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T52,T365,T53	Yes	T52,T365,T53	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_i2c2_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T303,T304,T309	Yes	T303,T304,T309	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T52,T365,T311	Yes	T62,T52,T365	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T52,*T365,*T53	Yes	T52,T365,T53	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T62,T52,T365	Yes	T62,T52,T365	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T155,T216,T217	Yes	T155,T216,T217	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T155,T216,T217	Yes	T155,T216,T217	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T62,T155,T216	Yes	T62,T155,T216	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T62,T155,T216	Yes	T62,T155,T216	INPUT
tl_pattgen_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T155,T216,T217	Yes	T155,T216,T217	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T155,T216,T217	Yes	T62,T155,T216	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T155,T216,T217	Yes	T62,T155,T216	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T155,*T216,*T217	Yes	T155,T216,T217	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T62,T155,T216	Yes	T62,T155,T216	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T218,T679,T693	Yes	T218,T679,T693	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T218,T679,T693	Yes	T218,T679,T693	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T62,T218,T679	Yes	T62,T218,T679	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T62,T218,T679	Yes	T62,T218,T679	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T218,T679,T693	Yes	T218,T679,T693	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T218,T679,T693	Yes	T62,T218,T679	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T218,T679,T693	Yes	T62,T218,T679	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T218,*T679,*T693	Yes	T218,T679,T693	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T62,T218,T679	Yes	T62,T218,T679	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T29,T36,T37	Yes	T29,T36,T37	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T36,T37	Yes	T62,T29,T3	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T29,T36,T37	Yes	T62,T29,T3	INPUT
tl_gpio_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T88	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T155,T49	Yes	T5,T155,T49	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T155,T49	Yes	T5,T155,T49	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T62,T155	Yes	T5,T62,T155	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T62,T155	Yes	T5,T62,T155	INPUT
tl_spi_device_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T5,T155,T49	Yes	T5,T155,T49	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T155,T49	Yes	T5,T155,T49	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T62,T155	Yes	T5,T155,T49	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T62,*T155	Yes	T5,T155,T49	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T62,T155	Yes	T5,T62,T155	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T155,T107,T251	Yes	T155,T107,T251	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T155,T107,T251	Yes	T155,T107,T251	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T62,T155,T107	Yes	T62,T155,T107	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T62,T155,T107	Yes	T62,T155,T107	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T155,T107,T251	Yes	T155,T107,T251	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T155,T107,T251	Yes	T62,T155,T107	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T107,T251,T713	Yes	T62,T155,T107	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T155,*T107,*T251	Yes	T155,T107,T251	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T62,T155,T107	Yes	T62,T155,T107	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T19	Yes	T4,T6,T19	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T151,T60	Yes	T18,T151,T60	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T18,T122,T151	Yes	T18,T122,T151	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T151,T152	Yes	T18,T151,T152	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T83,T85,T154	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T18,*T151,*T60	Yes	T18,T151,T60	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T9,*T80,*T81	Yes	T9,T80,T81	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T5,*T83,*T154	Yes	T5,T83,T154	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T5,*T20,*T153	Yes	T5,T20,T153	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T5,T20,T59	Yes	T5,T20,T59	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T59,T70	Yes	T20,T59,T70	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T84,*T297,*T298	Yes	T84,T297,T298	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T5,*T20,*T21	Yes	T5,T20,T21	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T20,T21	Yes	T5,T20,T21	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T145,T1,T2	Yes	T145,T1,T2	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T145,T1,T2	Yes	T145,T1,T2	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T6,*T19,*T65	Yes	T6,T19,T65	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T6,T19,T65	Yes	T6,T19,T65	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T182,T183,T184	Yes	T182,T183,T184	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T182,T54,T55	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T182,T54,T55	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T86,*T80,*T81	Yes	T86,T80,T81	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T182,*T183,*T184	Yes	T182,T115,T183	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T182,T54,T57	Yes	T182,T54,T57	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T87,*T255,*T202	Yes	T87,T255,T202	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T254,T85,T421	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T6,*T19,*T174	Yes	T6,T19,T174	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T6,T19,T174	Yes	T6,T19,T174	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T88	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T88	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T80	Yes	T85,T86,T80	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T252	Yes	T4,T6,T252	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T4,T6,T252	Yes	T4,T6,T252	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T71	Yes	T1,T2,T71	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T71	Yes	T1,T2,T71	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T13	Yes	T1,T2,T71	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T71	Yes	T1,T2,T62	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T71	Yes	T1,T2,T62	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T80,T81,T88	Yes	T80,T81,T82	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T85,*T80,*T81	Yes	T85,T80,T81	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T13	Yes	T1,T2,T71	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T62	Yes	T1,T2,T62	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T5,*T83,*T84	Yes	T5,T83,T84	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range