Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_timer 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 90.32 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : rv_timer
TotalCoveredPercent
Totals 30 30 100.00
Total Bits 292 292 100.00
Total Bits 0->1 146 146 100.00
Total Bits 1->0 146 146 100.00

Ports 30 30 100.00
Port Bits 292 292 100.00
Port Bits 0->1 146 146 100.00
Port Bits 1->0 146 146 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T155,T107,T251 Yes T155,T107,T251 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T155,T107,T251 Yes T155,T107,T251 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[8:0] Yes Yes *T80,*T81,*T82 Yes T80,T81,T82 INPUT
tl_i.a_address[19:9] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T5,*T83,*T84 Yes T5,T83,T84 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
tl_i.a_valid Yes Yes T62,T155,T107 Yes T62,T155,T107 INPUT
tl_o.a_ready Yes Yes T62,T155,T107 Yes T62,T155,T107 OUTPUT
tl_o.d_error Yes Yes T80,T81,T82 Yes T80,T81,T82 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T155,T107,T251 Yes T155,T107,T251 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T155,T107,T251 Yes T62,T155,T107 OUTPUT
tl_o.d_data[31:0] Yes Yes T107,T251,T713 Yes T62,T155,T107 OUTPUT
tl_o.d_sink Yes Yes T80,T81,T82 Yes T80,T81,T82 OUTPUT
tl_o.d_source[5:0] Yes Yes *T86,*T80,*T81 Yes T86,T80,T81 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T80,T81,T82 Yes T80,T81,T82 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T155,*T107,*T251 Yes T155,T107,T251 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T62,T155,T107 Yes T62,T155,T107 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T90,T91 Yes T62,T90,T91 INPUT
alert_rx_i[0].ping_n Yes Yes T90,T91,T93 Yes T91,T93,T256 INPUT
alert_rx_i[0].ping_p Yes Yes T91,T93,T256 Yes T90,T91,T93 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T90,T91 Yes T62,T90,T91 OUTPUT
intr_timer_expired_hart0_timer0_o Yes Yes T155,T107,T251 Yes T155,T107,T251 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%