Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T9,T293
0	1	Covered	T188,T293,T294
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T9,T293
1	Covered	T188,T9,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T9,T293
1	Covered	T188,T9,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T293,T294
1	1	Covered	T188,T9,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T9,T293
1	0	Covered	T188,T9,T293
1	1	Covered	T188,T293,T294

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T188,T9,T293

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T9,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T9,T293

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1052895364	1034895702	0	0
CheckNGreaterZero_A	2020	2020	0	0
GntImpliesReady_A	1052895364	8383	0	0
GntImpliesValid_A	1052895364	8383	0	0
GrantKnown_A	1052895364	1034895702	0	0
IdxKnown_A	1052895364	1034895702	0	0
IndexIsCorrect_A	1052895364	8383	0	0
NoReadyValidNoGrant_A	1052895364	0	0	0
Priority_A	1052895364	8383	0	0
ReadyAndValidImplyGrant_A	1052895364	8383	0	0
ReqAndReadyImplyGrant_A	1052895364	8383	0	0
ReqImpliesValid_A	1052895364	8383	0	0
ValidKnown_A	1052895364	1034895702	0	0
gen_data_port_assertion.DataFlow_A	1052895364	8383	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	1034895702	0	0
T4	215496	215440	0	0
T5	1090088	1090052	0	0
T6	1269806	1269064	0	0
T18	335646	335544	0	0
T19	316890	316788	0	0
T20	497214	496878	0	0
T61	81184	81074	0	0
T95	758648	758546	0	0
T96	660112	660010	0	0
T97	403268	403258	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2020	2020	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T61	2	2	0	0
T95	2	2	0	0
T96	2	2	0	0
T97	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	1034895702	0	0
T4	215496	215440	0	0
T5	1090088	1090052	0	0
T6	1269806	1269064	0	0
T18	335646	335544	0	0
T19	316890	316788	0	0
T20	497214	496878	0	0
T61	81184	81074	0	0
T95	758648	758546	0	0
T96	660112	660010	0	0
T97	403268	403258	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	1034895702	0	0
T4	215496	215440	0	0
T5	1090088	1090052	0	0
T6	1269806	1269064	0	0
T18	335646	335544	0	0
T19	316890	316788	0	0
T20	497214	496878	0	0
T61	81184	81074	0	0
T95	758648	758546	0	0
T96	660112	660010	0	0
T97	403268	403258	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	1034895702	0	0
T4	215496	215440	0	0
T5	1090088	1090052	0	0
T6	1269806	1269064	0	0
T18	335646	335544	0	0
T19	316890	316788	0	0
T20	497214	496878	0	0
T61	81184	81074	0	0
T95	758648	758546	0	0
T96	660112	660010	0	0
T97	403268	403258	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052895364	8383	0	0
T14	286784	0	0	0
T27	968042	0	0	0
T52	764976	0	0	0
T188	153782	2794	0	0
T293	0	2796	0	0
T294	0	2793	0	0
T381	319312	0	0	0
T382	751662	0	0	0
T383	195094	0	0	0
T384	253702	0	0	0
T385	150058	0	0	0
T386	327576	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T9,T293
0	1	Covered	T188,T293,T294
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T293,T294
1	Covered	T188,T9,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T293,T294
1	Covered	T188,T9,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T293,T294
1	1	Covered	T188,T293,T294

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T9,T293
1	0	Covered	T188,T293,T294
1	1	Covered	T188,T293,T294

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T188,T293,T294

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T293,T294

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T293,T294

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	526447682	517447851	0	0
CheckNGreaterZero_A	1010	1010	0	0
GntImpliesReady_A	526447682	5195	0	0
GntImpliesValid_A	526447682	5195	0	0
GrantKnown_A	526447682	517447851	0	0
IdxKnown_A	526447682	517447851	0	0
IndexIsCorrect_A	526447682	5195	0	0
NoReadyValidNoGrant_A	526447682	0	0	0
Priority_A	526447682	5195	0	0
ReadyAndValidImplyGrant_A	526447682	5195	0	0
ReqAndReadyImplyGrant_A	526447682	5195	0	0
ReqImpliesValid_A	526447682	5195	0	0
ValidKnown_A	526447682	517447851	0	0
gen_data_port_assertion.DataFlow_A	526447682	5195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	5195	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1731	0	0
T293	0	1734	0	0
T294	0	1730	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T188,T9,T293
0	1	Covered	T188,T293,T294
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T9,T293
1	Covered	T188,T9,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T188,T9,T293
1	Covered	T188,T9,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T188,T293,T294
1	1	Covered	T188,T9,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T188,T9,T293
1	0	Covered	T188,T9,T293
1	1	Covered	T188,T293,T294

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T188,T9,T293

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T9,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T188,T9,T293
0	Covered	T188,T9,T293

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	526447682	517447851	0	0
CheckNGreaterZero_A	1010	1010	0	0
GntImpliesReady_A	526447682	3188	0	0
GntImpliesValid_A	526447682	3188	0	0
GrantKnown_A	526447682	517447851	0	0
IdxKnown_A	526447682	517447851	0	0
IndexIsCorrect_A	526447682	3188	0	0
NoReadyValidNoGrant_A	526447682	0	0	0
Priority_A	526447682	3188	0	0
ReadyAndValidImplyGrant_A	526447682	3188	0	0
ReqAndReadyImplyGrant_A	526447682	3188	0	0
ReqImpliesValid_A	526447682	3188	0	0
ValidKnown_A	526447682	517447851	0	0
gen_data_port_assertion.DataFlow_A	526447682	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T61	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	517447851	0	0
T4	107748	107720	0	0
T5	545044	545026	0	0
T6	634903	634532	0	0
T18	167823	167772	0	0
T19	158445	158394	0	0
T20	248607	248439	0	0
T61	40592	40537	0	0
T95	379324	379273	0	0
T96	330056	330005	0	0
T97	201634	201629	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526447682	3188	0	0
T14	143392	0	0	0
T27	484021	0	0	0
T52	382488	0	0	0
T188	76891	1063	0	0
T293	0	1062	0	0
T294	0	1063	0	0
T381	159656	0	0	0
T382	375831	0	0	0
T383	97547	0	0	0
T384	126851	0	0	0
T385	75029	0	0	0
T386	163788	0	0	0