Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : chip_earlgrey_asic
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 80.00 100.00 95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.83 80.00 100.00 98.48



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.83 80.00 100.00 98.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.60 95.58 94.27 95.49 95.12 97.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
top_earlgrey 95.35 95.51 93.82 95.49 94.92 97.02
u_ast 93.28 93.28
u_padring 99.04 99.21 99.81 96.57 99.60 100.00
u_prim_usb_diff_rx 96.30 100.00 88.89 100.00

Line Coverage for Module : chip_earlgrey_asic
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T19

Toggle Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Totals 70 64 91.43
Total Bits 140 134 95.71
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 64 91.43

Ports 70 64 91.43
Port Bits 140 134 95.71
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 64 91.43

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
POR_N Yes Yes T5,T20,T21 Yes T4,T5,T6 INOUT
USB_P Yes Yes T33,T23,T34 Yes T33,T34,T35 INOUT
USB_N Yes Yes T33,T34,T35 Yes T33,T22,T23 INOUT
CC1 No No Yes T22,T23,T24 INOUT
CC2 No No Yes T22,T23,T24 INOUT
FLASH_TEST_VOLT No No Yes T22,T23,T24 INOUT
FLASH_TEST_MODE0 No No Yes T22,T23,T24 INOUT
FLASH_TEST_MODE1 No No Yes T22,T23,T24 INOUT
OTP_EXT_VOLT No No Yes T22,T23,T24 INOUT
SPI_HOST_D0 Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_D1 Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_D2 Yes Yes T27,T52,T197 Yes T22,T27,T52 INOUT
SPI_HOST_D3 Yes Yes T27,T52,T197 Yes T27,T52,T197 INOUT
SPI_HOST_CLK Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_CS_L Yes Yes T25,T26,T86 Yes T25,T26,T22 INOUT
SPI_DEV_D0 Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_D1 Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_D2 Yes Yes T27,T52,T197 Yes T27,T52,T197 INOUT
SPI_DEV_D3 Yes Yes T27,T14,T52 Yes T27,T14,T52 INOUT
SPI_DEV_CLK Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_CS_L Yes Yes T5,T94,T25 Yes T5,T94,T25 INOUT
IOR8 Yes Yes T4,T31,T32 Yes T4,T31,T32 INOUT
IOR9 Yes Yes T4,T31,T32 Yes T4,T31,T32 INOUT
IOA0 Yes Yes T28,T29,T3 Yes T28,T29,T3 INOUT
IOA1 Yes Yes T28,T29,T3 Yes T28,T29,T3 INOUT
IOA2 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA3 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA4 Yes Yes T151,T152,T29 Yes T151,T152,T29 INOUT
IOA5 Yes Yes T151,T152,T29 Yes T151,T152,T29 INOUT
IOA6 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA7 Yes Yes T29,T49,T3 Yes T29,T49,T3 INOUT
IOA8 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOB0 Yes Yes T52,T53,T44 Yes T23,T52,T53 INOUT
IOB1 Yes Yes T52,T53,T44 Yes T22,T52,T24 INOUT
IOB2 Yes Yes T52,T53,T201 Yes T52,T53,T201 INOUT
IOB3 Yes Yes T4,T31,T32 Yes T4,T31,T206 INOUT
IOB4 Yes Yes T114,T214,T215 Yes T114,T214,T215 INOUT
IOB5 Yes Yes T114,T214,T215 Yes T114,T214,T215 INOUT
IOB6 Yes Yes T4,T29,T31 Yes T4,T29,T31 INOUT
IOB7 Yes Yes T1,T2,T29 Yes T1,T2,T29 INOUT
IOB8 Yes Yes T4,T29,T31 Yes T29,T31,T36 INOUT
IOB9 Yes Yes T4,T29,T31 Yes T29,T31,T32 INOUT
IOB10 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOB11 Yes Yes T29,T216,T217 Yes T29,T216,T217 INOUT
IOB12 Yes Yes T29,T216,T217 Yes T29,T216,T217 INOUT
IOC0 Yes Yes T5,T54,T57 Yes T5,T263,T204 INOUT
IOC1 Yes Yes T5,T94,T204 Yes T5,T204,T23 INOUT
IOC2 Yes Yes T5,T94,T204 Yes T5,T204,T205 INOUT
IOC3 Yes Yes T18,T219,T220 Yes T18,T219,T220 INOUT
IOC4 Yes Yes T18,T54,T57 Yes T18,T54,T57 INOUT
IOC5 Yes Yes T5,T76,T73 Yes T5,T72,T83 INOUT
IOC6 Yes Yes T61,T59,T114 Yes T61,T59,T114 INOUT
IOC7 Yes Yes T4,T31,T206 Yes T4,T31,T32 INOUT
IOC8 Yes Yes T83,T76,T349 Yes T5,T76,T73 INOUT
IOC9 Yes Yes T4,T29,T31 Yes T4,T29,T31 INOUT
IOC10 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOC11 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOC12 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOR0 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR1 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR2 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR3 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR4 Yes Yes T5,T59,T60 Yes T5,T61,T59 INOUT
IOR5 Yes Yes T29,T31,T32 Yes T29,T31,T32 INOUT
IOR6 Yes Yes T29,T31,T36 Yes T29,T31,T32 INOUT
IOR7 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR10 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR11 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR12 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR13 Yes Yes T1,T2,T29 Yes T1,T2,T29 INOUT

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T19

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 66 64 96.97
Total Bits 132 130 98.48
Total Bits 0->1 66 66 100.00
Total Bits 1->0 66 64 96.97

Ports 66 64 96.97
Port Bits 132 130 98.48
Port Bits 0->1 66 66 100.00
Port Bits 1->0 66 64 96.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
POR_N Yes Yes T5,T20,T21 Yes T4,T5,T6 INOUT
USB_P Yes Yes T33,T23,T34 Yes T33,T34,T35 INOUT
USB_N Yes Yes T33,T34,T35 Yes T33,T22,T23 INOUT
CC1 No No Yes T22,T23,T24 INOUT
CC2 No No Yes T22,T23,T24 INOUT
FLASH_TEST_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0 Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_D1 Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_D2 Yes Yes T27,T52,T197 Yes T22,T27,T52 INOUT
SPI_HOST_D3 Yes Yes T27,T52,T197 Yes T27,T52,T197 INOUT
SPI_HOST_CLK Yes Yes T25,T26,T27 Yes T25,T26,T27 INOUT
SPI_HOST_CS_L Yes Yes T25,T26,T86 Yes T25,T26,T22 INOUT
SPI_DEV_D0 Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_D1 Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_D2 Yes Yes T27,T52,T197 Yes T27,T52,T197 INOUT
SPI_DEV_D3 Yes Yes T27,T14,T52 Yes T27,T14,T52 INOUT
SPI_DEV_CLK Yes Yes T5,T49,T94 Yes T5,T49,T94 INOUT
SPI_DEV_CS_L Yes Yes T5,T94,T25 Yes T5,T94,T25 INOUT
IOR8 Yes Yes T4,T31,T32 Yes T4,T31,T32 INOUT
IOR9 Yes Yes T4,T31,T32 Yes T4,T31,T32 INOUT
IOA0 Yes Yes T28,T29,T3 Yes T28,T29,T3 INOUT
IOA1 Yes Yes T28,T29,T3 Yes T28,T29,T3 INOUT
IOA2 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA3 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA4 Yes Yes T151,T152,T29 Yes T151,T152,T29 INOUT
IOA5 Yes Yes T151,T152,T29 Yes T151,T152,T29 INOUT
IOA6 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOA7 Yes Yes T29,T49,T3 Yes T29,T49,T3 INOUT
IOA8 Yes Yes T29,T3,T36 Yes T29,T3,T36 INOUT
IOB0 Yes Yes T52,T53,T44 Yes T23,T52,T53 INOUT
IOB1 Yes Yes T52,T53,T44 Yes T22,T52,T24 INOUT
IOB2 Yes Yes T52,T53,T201 Yes T52,T53,T201 INOUT
IOB3 Yes Yes T4,T31,T32 Yes T4,T31,T206 INOUT
IOB4 Yes Yes T114,T214,T215 Yes T114,T214,T215 INOUT
IOB5 Yes Yes T114,T214,T215 Yes T114,T214,T215 INOUT
IOB6 Yes Yes T4,T29,T31 Yes T4,T29,T31 INOUT
IOB7 Yes Yes T1,T2,T29 Yes T1,T2,T29 INOUT
IOB8 Yes Yes T4,T29,T31 Yes T29,T31,T36 INOUT
IOB9 Yes Yes T4,T29,T31 Yes T29,T31,T32 INOUT
IOB10 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOB11 Yes Yes T29,T216,T217 Yes T29,T216,T217 INOUT
IOB12 Yes Yes T29,T216,T217 Yes T29,T216,T217 INOUT
IOC0 Yes Yes T5,T54,T57 Yes T5,T263,T204 INOUT
IOC1 Yes Yes T5,T94,T204 Yes T5,T204,T23 INOUT
IOC2 Yes Yes T5,T94,T204 Yes T5,T204,T205 INOUT
IOC3 Yes Yes T18,T219,T220 Yes T18,T219,T220 INOUT
IOC4 Yes Yes T18,T54,T57 Yes T18,T54,T57 INOUT
IOC5 Yes Yes T5,T76,T73 Yes T5,T72,T83 INOUT
IOC6 Yes Yes T61,T59,T114 Yes T61,T59,T114 INOUT
IOC7 Yes Yes T4,T31,T206 Yes T4,T31,T32 INOUT
IOC8 Yes Yes T83,T76,T349 Yes T5,T76,T73 INOUT
IOC9 Yes Yes T4,T29,T31 Yes T4,T29,T31 INOUT
IOC10 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOC11 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOC12 Yes Yes T29,T36,T218 Yes T29,T36,T218 INOUT
IOR0 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR1 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR2 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR3 Yes Yes T5,T61,T59 Yes T5,T61,T59 INOUT
IOR4 Yes Yes T5,T59,T60 Yes T5,T61,T59 INOUT
IOR5 Yes Yes T29,T31,T32 Yes T29,T31,T32 INOUT
IOR6 Yes Yes T29,T31,T36 Yes T29,T31,T32 INOUT
IOR7 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR10 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR11 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR12 Yes Yes T29,T36,T37 Yes T29,T36,T37 INOUT
IOR13 Yes Yes T1,T2,T29 Yes T1,T2,T29 INOUT

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