Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
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Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_chip_env_0.1/chip_env_cov.sv

65 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
aes_fatal_fault 100.00 1 100 1 64 64
aes_recov_ctrl_update_err 100.00 1 100 1 64 64
aon_timer_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_recov_fault 100.00 1 100 1 64 64
csrng_fatal_alert 100.00 1 100 1 64 64
csrng_recov_alert 100.00 1 100 1 64 64
edn0_fatal_alert 100.00 1 100 1 64 64
edn0_recov_alert 100.00 1 100 1 64 64
edn1_fatal_alert 100.00 1 100 1 64 64
edn1_recov_alert 100.00 1 100 1 64 64
entropy_src_fatal_alert 100.00 1 100 1 64 64
entropy_src_recov_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_err 100.00 1 100 1 64 64
flash_ctrl_fatal_prim_flash_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_std_err 100.00 1 100 1 64 64
flash_ctrl_recov_err 100.00 1 100 1 64 64
flash_ctrl_recov_prim_flash_alert 100.00 1 100 1 64 64
gpio_fatal_fault 100.00 1 100 1 64 64
hmac_fatal_fault 100.00 1 100 1 64 64
i2c0_fatal_fault 100.00 1 100 1 64 64
i2c1_fatal_fault 100.00 1 100 1 64 64
i2c2_fatal_fault 100.00 1 100 1 64 64
keymgr_fatal_fault_err 100.00 1 100 1 64 64
keymgr_recov_operation_err 100.00 1 100 1 64 64
kmac_fatal_fault_err 100.00 1 100 1 64 64
kmac_recov_operation_err 100.00 1 100 1 64 64
lc_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
lc_ctrl_fatal_prog_error 100.00 1 100 1 64 64
lc_ctrl_fatal_state_error 100.00 1 100 1 64 64
otbn_fatal 100.00 1 100 1 64 64
otbn_recov 100.00 1 100 1 64 64
otp_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
otp_ctrl_fatal_check_error 100.00 1 100 1 64 64
otp_ctrl_fatal_macro_error 100.00 1 100 1 64 64
otp_ctrl_fatal_prim_otp_alert 100.00 1 100 1 64 64
otp_ctrl_recov_prim_otp_alert 100.00 1 100 1 64 64
pattgen_fatal_fault 100.00 1 100 1 64 64
pinmux_aon_fatal_fault 100.00 1 100 1 64 64
pwm_aon_fatal_fault 100.00 1 100 1 64 64
pwrmgr_aon_fatal_fault 100.00 1 100 1 64 64
rom_ctrl_fatal 100.00 1 100 1 64 64
rstmgr_aon_fatal_cnsty_fault 100.00 1 100 1 64 64
rstmgr_aon_fatal_fault 100.00 1 100 1 64 64
rv_core_ibex_fatal_hw_err 100.00 1 100 1 64 64
rv_core_ibex_fatal_sw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_hw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_sw_err 100.00 1 100 1 64 64
rv_dm_fatal_fault 100.00 1 100 1 64 64
rv_plic_fatal_fault 100.00 1 100 1 64 64
rv_timer_fatal_fault 100.00 1 100 1 64 64
sensor_ctrl_aon_fatal_alert 100.00 1 100 1 64 64
sensor_ctrl_aon_recov_alert 100.00 1 100 1 64 64
spi_device_fatal_fault 100.00 1 100 1 64 64
spi_host0_fatal_fault 100.00 1 100 1 64 64
spi_host1_fatal_fault 100.00 1 100 1 64 64
sram_ctrl_main_fatal_error 100.00 1 100 1 64 64
sram_ctrl_ret_aon_fatal_error 100.00 1 100 1 64 64
sysrst_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
uart0_fatal_fault 100.00 1 100 1 64 64
uart1_fatal_fault 100.00 1 100 1 64 64
uart2_fatal_fault 100.00 1 100 1 64 64
uart3_fatal_fault 100.00 1 100 1 64 64
usbdev_fatal_fault 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance adc_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_recov_ctrl_update_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_recov_ctrl_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_recov_ctrl_update_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aon_timer_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aon_timer_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_recov_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_recov_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_recov_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_std_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_std_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_std_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : gpio_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance gpio_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : hmac_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance hmac_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_prog_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_prog_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_prog_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_state_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_state_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_state_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_recov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_recov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_recov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_check_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_check_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_check_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_macro_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_macro_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_macro_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_recov_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_recov_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_recov_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pattgen_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pattgen_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pinmux_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pinmux_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwm_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwm_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwrmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwrmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rom_ctrl_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rom_ctrl_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_cnsty_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_cnsty_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_cnsty_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_dm_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_dm_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_plic_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_plic_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_timer_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_timer_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_device_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_device_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_main_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_main_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_ret_aon_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_ret_aon_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sysrst_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sysrst_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart3_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart3_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : usbdev_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance usbdev_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2867 1 T262 530 T80 35 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 119563 1 T16 603 T61 585 T62 1438


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 176 1 T80 44 T56 1 T82 28


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 711 1 T80 46 T56 1 T82 32


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8544 1 T80 39 T314 815 T352 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 827 1 T704 102 T705 106 T80 37


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5798 1 T245 1090 T80 34 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 178 1 T660 1 T80 38 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4779 1 T61 1711 T80 52 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 187 1 T660 1 T80 31 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6958 1 T665 1130 T80 24 T666 1718


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 167 1 T80 38 T56 1 T82 32


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8678 1 T257 1718 T392 1713 T80 37


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 198 1 T80 35 T56 1 T82 49


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8536 1 T164 304 T80 37 T95 1713


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4727 1 T80 37 T56 1 T82 32


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1904 1 T80 36 T221 1729 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 386 1 T164 10 T104 36 T244 5


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 177 1 T80 34 T56 1 T82 42


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2831 1 T80 43 T697 814 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5952 1 T699 1172 T80 33 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3391 1 T80 37 T387 526 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2363 1 T80 42 T732 813 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2081 1 T263 516 T80 48 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6474 1 T289 1719 T80 30 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 212 1 T80 47 T56 1 T82 52


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 108232 1 T16 603 T61 585 T62 1438


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 188 1 T80 46 T56 1 T82 36


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1738 1 T80 30 T56 1 T82 36


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1923 1 T32 1 T80 45 T100 570


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3451 1 T32 1 T80 39 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1392256 1 T16 603 T20 106219 T61 585


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 183 1 T32 1 T288 1 T80 27


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1717 1 T80 38 T56 1 T154 516


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 50216 1 T16 282 T61 278 T62 682


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 994 1 T80 30 T56 1 T82 31


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6848 1 T32 1 T80 42 T155 524


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 200 1 T80 41 T56 1 T82 47


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1209 1 T80 38 T98 522 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2843 1 T32 1 T80 38 T81 812


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2861 1 T2 1 T80 39 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8941 1 T16 823 T42 497 T62 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7050 1 T413 1089 T409 1718 T2 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3123 1 T439 818 T2 1 T80 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1837 1 T80 39 T353 823 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 37885 1 T227 1733 T219 794 T220 2852


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 11535 1 T2 1 T80 42 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 125 1 T80 18 T56 1 T82 13


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 275 1 T67 1 T2 2 T80 36


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2460 1 T80 29 T700 1189 T82 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8677 1 T433 1736 T32 1 T80 44


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2648 1 T2 1 T359 811 T80 38


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5117 1 T135 108 T80 42 T130 120


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 12559 1 T135 71 T80 45 T128 1407


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2051 1 T32 1 T80 40 T92 530


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 10711 1 T324 1112 T80 40 T737 1677


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7455 1 T2 1 T80 35 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3636 1 T32 1 T80 46 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 191 1 T32 1 T80 43 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 183 1 T32 1 T2 1 T80 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1548 1 T80 49 T56 1 T82 35


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 705 1 T80 37 T56 1 T82 31


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4212 1 T710 506 T80 32 T712 816


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4193 1 T80 37 T711 817 T56 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4967 1 T106 1304 T80 43 T56 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%